Abstract: Methods of forming decoupling capacitors in interconnect structures formed on backsides of semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a device includes a device layer including a first transistor; a first interconnect structure on a front-side of the device layer; a second interconnect structure on a backside of the device layer, the second interconnect structure including a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a first conductive layer including a first conductive line electrically connected to the source/drain region of the first transistor through the contact; and a second dielectric layer adjacent the first conductive line, the second dielectric layer including a material having a k-value greater than 7.0, a first decoupling capacitor including the first conductive line and the second dielectric layer.

Abstract: Methods of performing backside etching processes on source/drain regions and gate structures of semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a first interconnect structure on a front-side of the first transistor structure; and a second interconnect structure on a backside of the first transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and first spacers along sidewalls of the contact between the contact and the first dielectric layer, sidewalls of the first spacers facing the first dielectric layer being aligned with sidewalls of the source/drain region of the first transistor structure.

Abstract: In an embodiment, a device includes: a first interconnect structure including metallization patterns; a second interconnect structure including a power rail; a device layer between the first interconnect structure and the second interconnect structure, the device layer including a first transistor, the first transistor including an epitaxial source/drain region; and a conductive via extending through the device layer, the conductive via connecting the power rail to the metallization patterns, the conductive via contacting the epitaxial source/drain region.

Abstract: The present disclosure provides embodiments of semiconductor devices. A semiconductor device according to the present disclosure include an elongated semiconductor member surrounded by an isolation feature and extending lengthwise along a first direction, a first source/drain feature and a second source/drain feature over a top surface of the elongated semiconductor member, a vertical stack of channel members each extending lengthwise between the first source/drain feature and the second source/drain feature along the first direction, a gate structure wrapping around each of the channel members, an epitaxial layer deposited on the bottom surface of the elongated semiconductor member, a silicide layer disposed on the epitaxial layer, and a conductive layer disposed on the silicide layer.

Abstract: Methods of performing backside etching processes on source/drain regions and gate structures of semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a first interconnect structure on a front-side of the first transistor structure; and a second interconnect structure on a backside of the first transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and first spacers along sidewalls of the contact between the contact and the first dielectric layer, sidewalls of the first spacers facing the first dielectric layer being aligned with sidewalls of the source/drain region of the first transistor structure.

Abstract: A semiconductor structure includes a first transistor having a first source/drain (S/D) feature and a first gate; a second transistor having a second S/D feature and a second gate; a multi-layer interconnection disposed over the first and the second transistors; a signal interconnection under the first and the second transistors; and a power rail under the signal interconnection and electrically isolated from the signal interconnection, wherein the signal interconnection electrically connects one of the first S/D feature and the first gate to one of the second S/D feature and the second gate.

Abstract: The present disclosure provides an integrated circuit that includes a circuit formed on a semiconductor substrate; and a de-cap device formed on the semiconductor substrate and integrated with the circuit. The de-cap device includes a filed-effect transistor (FET) that further includes a source and a drain connected through contact features landing on the source and drain, respectively; a gate stack overlying a channel and interposed between the source and the drain; and a doped feature disposed underlying the channel and connecting to the source and the drain, wherein the doped feature is doped with a dopant of a same type of the source and the drain.

Abstract: In an embodiment, a device includes: a first interconnect structure including metallization patterns; a second interconnect structure including a power rail; a device layer between the first interconnect structure and the second interconnect structure, the device layer including a first transistor, the first transistor including an epitaxial source/drain region; and a conductive via extending through the device layer, the conductive via connecting the power rail to the metallization patterns, the conductive via contacting the epitaxial source/drain region.

Abstract: The present disclosure provides embodiments of semiconductor devices. A semiconductor device according to the present disclosure include an elongated semiconductor member surrounded by an isolation feature and extending lengthwise along a first direction, a first source/drain feature and a second source/drain feature over a top surface of the elongated semiconductor member, a vertical stack of channel members each extending lengthwise between the first source/drain feature and the second source/drain feature along the first direction, a gate structure wrapping around each of the channel members, an epitaxial layer deposited on the bottom surface of the elongated semiconductor member, a silicide layer disposed on the epitaxial layer, and a conductive layer disposed on the silicide layer.

Abstract: An integrated circuit (IC) structure includes a gate structure, a source epitaxial structure, a drain epitaxial structure, a front-side interconnection structure, a backside dielectric layer, an epitaxial regrowth layer, and a backside via. The source epitaxial structure and the drain epitaxial structure are respectively on opposite sides of the gate structure. The front-side interconnection structure is over a front-side of the source epitaxial structure and a front-side of the drain epitaxial structure. The backside dielectric layer is over a backside of the source epitaxial structure and a backside of the drain epitaxial structure. The epitaxial regrowth layer is on the backside of a first one of the source epitaxial structure and the drain epitaxial structure. The backside via extends through the backside dielectric layer and overlaps the epitaxial regrowth layer.

Abstract: A device includes a semiconductor substrate, a source feature and a drain feature over the semiconductor substrate, a stack of semiconductor layers interposed between the source feature and the drain feature, a gate portion, and an inner spacer of a dielectric material. The gate portion is between two vertically adjacent layers of the stack of semiconductor layers and between the source feature and the drain feature. Moreover, the gate portion has a first sidewall surface and a second sidewall surface opposing the first sidewall surface. The inner spacer is on the first sidewall surface and between the gate portion and the drain feature. The second sidewall surface is in direct contact with the source feature.

Abstract: The disclosure relates to a linear actuator including a base, a linear motor, a load cell and a rotary motor. The linear motor is disposed on the base and includes a fixed coil module and a movable magnetic backplane. The fixed coil module is fixed on the base, and the movable magnetic backplane is configured to slide relative to the fixed coil module along a first direction. The rotary motor is rotated around a central axis in parallel with the first direction. The load cell has two opposite sides parallel to the first direction, respectively. The movable magnetic backplane of the linear motor and the rotary motor are connected to the two opposite sides of the load cell, respectively. The load cell is subjected to a force applied thereto by the rotary motor and parallel to the first direction, and configured to convert the force into an electrical signal.

Abstract: A light-emitting diode (LED) sub-chip and a method of producing the same are provided. The LED sub-chip comprises an epitaxial layer disposed on a growth substrate, where the epitaxial layer comprises a plurality of electrodes. The groove disposed between the LED sub-chip and a second LED sub-chip, where the groove penetrates through the epitaxial layer separating the two sub-chips. The bridge insulating layer at least partially covering a sidewall of the groove, where the sidewall comprises a first surface and a second surface above the first surface, where the texture of the second surface is less granular than a texture of the first surface. The bridge electrode on the bridge insulating layer, where the bridge electrode connects respective electrodes of the two sub-chips at the first surface.

Abstract: A method for measuring temperature is used to obtain a room temperature of a room. The method for measuring temperature includes: obtaining a first temperature inside an operating area in a portable electronic device in the room; obtaining a second temperature outside the operating area in the portable electronic device by a first temperature sensor; calculating a temperature difference between the first temperature and the second temperature; obtaining a compensation temperature according to the temperature difference and a compensation temperature table; and calculating the room temperature according to the second temperature and the compensation temperature.

Abstract: A magnetic pole detection circuit includes a multi-phase voltage divider unit, a filter unit, a DC level compensation unit, an amplifying unit, and a hysteresis comparison unit. The multi-phase voltage divider unit is configured to detect a back electromotive force (EMF) signal of a multi-phase motor. The filter unit is configured to filter the back EMF signal to generate a filtered signal. The DC level compensation unit is configured to compensate a DC level of the filtered signal to generate a compensation signal. The amplifying unit is configured to amplify the compensation signal to generate an amplified signal. The hysteresis comparison unit is configured to generate a zero-crossing point signal according to the amplified signal and a reference signal. The zero-crossing point signal is adapted to control an excitation mode of the multi-phase motor.

Abstract: Systems, devices, media, and methods are presented for graphical icon identification within an image or video stream. The systems and methods receive an image including a graphical icon. The systems and methods identify a set of proposed regions of the image, at least one proposed region of the set of proposed regions containing the graphical icon and extract a set of semantic features for each proposed region of the set of proposed regions. Based on the set of semantic features of the set of proposed regions, the systems and methods identify a set of proposed icons corresponding to the graphical icon included in the image and determine a match between the graphical icon and at least one proposed icon of the set of proposed icons.

Abstract: A semiconductor structure includes a first transistor having a first source/drain (S/D) feature and a first gate; a second transistor having a second S/D feature and a second gate; a multi-layer interconnection disposed over the first and the second transistors; a signal interconnection under the first and the second transistors; and a power rail under the signal interconnection and electrically isolated from the signal interconnection, wherein the signal interconnection electrically connects one of the first S/D feature and the first gate to one of the second S/D feature and the second gate.

Abstract: An integrated circuit (IC) structure includes a gate structure, a source epitaxial structure, a drain epitaxial structure, a front-side interconnection structure, a backside dielectric layer, an epitaxial regrowth layer, and a backside via. The source epitaxial structure and the drain epitaxial structure are respectively on opposite sides of the gate structure. The front-side interconnection structure is over a front-side of the source epitaxial structure and a front-side of the drain epitaxial structure. The backside dielectric layer is over a backside of the source epitaxial structure and a backside of the drain epitaxial structure. The epitaxial regrowth layer is on the backside of a first one of the source epitaxial structure and the drain epitaxial structure. The backside via extends through the backside dielectric layer and overlaps the epitaxial regrowth layer.

Abstract: Systems, methods, devices, computer readable instruction media, and other embodiments are described for automated image processing and insight presentation. One embodiment involves receiving a plurality of ephemeral content messages from a plurality of client devices, and processing the messages to identify content associated with at least a first content type. A set of analysis data associated with the first content type is then generated from the messages, and portions of the messages associated with the first content type are processed to generate a first content collection. The first content collection and the set of analysis data are then communicated to a client device configured for a display interface comprising the first content collection and a representation of at least a portion of the set of analysis data.

Abstract: A device includes a vertical stack of semiconductor nanostructures, a gate structure, a first epitaxial region and a dielectric structure. The gate structure wraps around the semiconductor nanostructures. The first epitaxial region laterally abuts a first semiconductor nanostructure of the semiconductor nanostructures. The dielectric structure laterally abuts a second semiconductor nanostructure of the semiconductor nanostructures and vertically abuts the first epitaxial region.