Patents by Inventor Xusheng Bao

Xusheng Bao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9478485
    Abstract: A semiconductor device has a first semiconductor die. A first interconnect structure, such as a conductive pillar including a bump formed over the conductive pillar, and second interconnect structure are formed in a peripheral region of the first semiconductor die. A second semiconductor die is disposed over the first semiconductor die between the first interconnect structure and the second interconnect structure. A height of the second semiconductor die is less than a height of the first interconnect structure. A footprint of the second semiconductor die is smaller than a central region of the first semiconductor die. An encapsulant is deposited over the first semiconductor die and second semiconductor die. Alternatively, the second semiconductor die is disposed over a semiconductor package including a plurality of interconnect structures. External connectivity from the single side fo-WLCSP is performed without the use of conductive vias to provide a high throughput and device reliability.
    Type: Grant
    Filed: April 24, 2014
    Date of Patent: October 25, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: XuSheng Bao, KwokKeung Szeto
  • Patent number: 9437552
    Abstract: A plurality of semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. A portion of the encapsulant is designated as a saw street between the die, and a portion of the encapsulant is designated as a substrate edge around a perimeter of the encapsulant. The carrier is removed. A first insulating layer is formed over the die, saw street, and substrate edge. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first conductive layer and first insulating layer. The encapsulant is singulated through the first insulating layer and saw street to separate the semiconductor die. A channel or net pattern can be formed in the first insulating layer on opposing sides of the saw street, or the first insulating layer covers the entire saw street and molding area around the semiconductor die.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: September 6, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Kang Chen, Jianmin Fang, Xia Feng, Xusheng Bao
  • Patent number: 9401331
    Abstract: A semiconductor device is made by forming a first conductive layer over a carrier. The first conductive layer has a first area electrically isolated from a second area of the first conductive layer. A conductive pillar is formed over the first area of the first conductive layer. A semiconductor die or component is mounted to the second area of the first conductive layer. A first encapsulant is deposited over the semiconductor die and around the conductive pillar. A first interconnect structure is formed over the first encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The carrier is removed. A portion of the first conductive layer is removed. The remaining portion of the first conductive layer includes an interconnect line and UBM pad. A second interconnect structure is formed over a remaining portion of the first conductive layer is removed.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: July 26, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Xusheng Bao, Kang Chen, Jianmin Fang
  • Patent number: 9397058
    Abstract: A semiconductor device has a semiconductor wafer with a first conductive layer formed over a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and first conductive layer. A second conductive layer is formed over the first insulating layer and first conductive layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A plurality of openings is formed in the second insulating layer in a bump formation area of the semiconductor wafer to expose the second conductive layer and reduce adverse effects of electro-migration. The openings are separated by portions of the second insulating layer. A UBM layer is formed over the openings in the second insulating layer in the bump formation area electrically connected to the second conductive layer. A bump is formed over the UBM layer.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: July 19, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Xusheng Bao, Ma Phoo Pwint Hlaing, Jian Zuo
  • Publication number: 20160141238
    Abstract: A semiconductor device has a semiconductor die with an encapsulant deposited over and around the semiconductor die. An interconnect structure is formed over a first surface of the encapsulant. An opening is formed from a second surface of the encapsulant to the first surface of the encapsulant to expose a surface of the interconnect structure. A bump is formed recessed within the opening and disposed over the surface of the interconnect structure. A semiconductor package is provided. The semiconductor package is disposed over the second surface of the encapsulant and electrically connected to the bump. A plurality of interconnect structures is formed over the semiconductor package to electrically connect the semiconductor package to the bump. The semiconductor package includes a memory device. The semiconductor device includes a height less than 1 millimeter. The opening includes a tapered sidewall formed by laser direct ablation.
    Type: Application
    Filed: January 27, 2016
    Publication date: May 19, 2016
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Seung Wook Yoon, Jose A. Caparas, Yaojian Lin, Pandi C. Marimuthu, Kang Chen, Xusheng Bao, Jianmin Fang
  • Patent number: 9293401
    Abstract: A semiconductor device has a semiconductor die with an encapsulant deposited over and around the semiconductor die. An interconnect structure is formed over a first surface of the encapsulant. An opening is formed from a second surface of the encapsulant to the first surface of the encapsulant to expose a surface of the interconnect structure. A bump is formed recessed within the opening and disposed over the surface of the interconnect structure. A semiconductor package is provided. The semiconductor package is disposed over the second surface of the encapsulant and electrically connected to the bump. A plurality of interconnect structures is formed over the semiconductor package to electrically connect the semiconductor package to the bump. The semiconductor package includes a memory device. The semiconductor device includes a height less than 1 millimeter. The opening includes a tapered sidewall formed by laser direct ablation.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: March 22, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Seung Wook Yoon, Jose A. Caparas, Yaojian Lin, Pandi C. Marimuthu, Kang Chen, Xusheng Bao, Jianmin Fang
  • Patent number: 9252172
    Abstract: A semiconductor device has a substrate containing a transparent or translucent material. A spacer is mounted to the substrate. A first semiconductor die has an active region and first conductive vias electrically connected to the active region. The active region can include a sensor responsive to light received through the substrate. The first die is mounted to the spacer with the active region positioned over an opening in the spacer and oriented toward the substrate. An encapsulant is deposited over the first die and substrate. An interconnect structure is formed over the encapsulant and first die. The interconnect structure is electrically connected through the first conductive vias to the active region. A second semiconductor die having second conductive vias can be mounted to the first die with the first conductive vias electrically connected to the second conductive vias.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: February 2, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Seng Guan Chow, Lee Sun Lim, Rui Huang, Xusheng Bao, Ma Phoo Pwint Hlaing
  • Patent number: 9236278
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a dummy-die paddle having a first inactive side facing up, a second inactive side facing down; forming an insulator in a single continuous structure around and in direct contact with the first inactive side; and mounting an integrated circuit over the dummy-die paddle and the insulator, the integrated circuit and the dummy-die paddle having the same coefficient of thermal expansion as the dummy-die paddle.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: January 12, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: Rui Huang, Xusheng Bao, Kang Chen, Yung Kuan Hsiao, Hin Hwa Goh
  • Patent number: 9171769
    Abstract: A semiconductor device has a plurality of semiconductor die mounted active surface to a carrier. An encapsulant is deposited over semiconductor die and carrier. Openings are formed through a surface of the encapsulant to divide the encapsulant into discontinuous segments. The openings have straight or beveled sidewalls. The openings can be formed partially through the surface of the encapsulant in an area between the semiconductor die. The openings can be formed partially through the surface of the encapsulant over the semiconductor die. The openings can be formed through the encapsulant in an area between the semiconductor die. A portion of the surface of the encapsulant is removed down to a bottom of the openings. The carrier is removed. An interconnect structure is formed over the encapsulant and the semiconductor die. The encapsulant is cured prior to or after forming the openings.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: October 27, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Seng Guan Chow, Lee Sun Lim, Rui Huang, Xusheng Bao, Ma Phoo Pwint Hlaing
  • Patent number: 9142522
    Abstract: A semiconductor device has a semiconductor wafer with a plurality of semiconductor die. A first conductive layer is formed over a surface of the wafer. A first insulating layer is formed over the surface of the wafer and first conductive layer. A second conductive layer has first and second segments formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A UBM layer is formed over the second insulating layer and the first segment of the second conductive layer. A first bump is formed over the UBM layer. The first bump is electrically connected to the second segment and electrically isolated from the first segment of the second conductive layer. A second bump is formed over the surface of the wafer and electrically connected to the first segment of the second conductive layer.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: September 22, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Xusheng Bao, Ma Phoo Pwint Hlaing, Jian Zuo
  • Publication number: 20150091165
    Abstract: A semiconductor device has a semiconductor wafer with a first conductive layer formed over a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and first conductive layer. A second conductive layer is formed over the first insulating layer and first conductive layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A plurality of openings is formed in the second insulating layer in a bump formation area of the semiconductor wafer to expose the second conductive layer and reduce adverse effects of electro-migration. The openings are separated by portions of the second insulating layer. A UBM layer is formed over the openings in the second insulating layer in the bump formation area electrically connected to the second conductive layer. A bump is formed over the UBM layer.
    Type: Application
    Filed: December 8, 2014
    Publication date: April 2, 2015
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Xusheng Bao, Ma Phoo Pwint Hlaing, Jian Zuo
  • Patent number: 8963326
    Abstract: A semiconductor device has a semiconductor wafer with a first conductive layer formed over a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and first conductive layer. A second conductive layer is formed over the first insulating layer and first conductive layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A plurality of openings is formed in the second insulating layer in a bump formation area of the semiconductor wafer to expose the second conductive layer and reduce adverse effects of electro-migration. The openings are separated by portions of the second insulating layer. A UBM layer is formed over the openings in the second insulating layer in the bump formation area electrically connected to the second conductive layer. A bump is formed over the UBM layer.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: February 24, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Xusheng Bao, Ma Phoo Pwint Hlaing, Jian Zuo
  • Publication number: 20150001709
    Abstract: A semiconductor device has a first semiconductor die. A first interconnect structure, such as a conductive pillar including a bump formed over the conductive pillar, and second interconnect structure are formed in a peripheral region of the first semiconductor die. A second semiconductor die is disposed over the first semiconductor die between the first interconnect structure and the second interconnect structure. A height of the second semiconductor die is less than a height of the first interconnect structure. A footprint of the second semiconductor die is smaller than a central region of the first semiconductor die. An encapsulant is deposited over the first semiconductor die and second semiconductor die. Alternatively, the second semiconductor die is disposed over a semiconductor package including a plurality of interconnect structures. External connectivity from the single side fo-WLCSP is performed without the use of conductive vias to provide a high throughput and device reliability.
    Type: Application
    Filed: April 24, 2014
    Publication date: January 1, 2015
    Applicant: STATS ChipPAC, Ltd.
    Inventors: XuSheng Bao, KwokKeung Szeto
  • Publication number: 20140339683
    Abstract: A plurality of semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. A portion of the encapsulant is designated as a saw street between the die, and a portion of the encapsulant is designated as a substrate edge around a perimeter of the encapsulant. The carrier is removed. A first insulating layer is formed over the die, saw street, and substrate edge. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first conductive layer and first insulating layer. The encapsulant is singulated through the first insulating layer and saw street to separate the semiconductor die. A channel or net pattern can be formed in the first insulating layer on opposing sides of the saw street, or the first insulating layer covers the entire saw street and molding area around the semiconductor die.
    Type: Application
    Filed: August 1, 2014
    Publication date: November 20, 2014
    Inventors: Yaojian Lin, Kang Chen, Jianmin Fang, Xia Feng, Xusheng Bao
  • Patent number: 8878359
    Abstract: A plurality of semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. A portion of the encapsulant is designated as a saw street between the die, and a portion of the encapsulant is designated as a substrate edge around a perimeter of the encapsulant. The carrier is removed. A first insulating layer is formed over the die, saw street, and substrate edge. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first conductive layer and first insulating layer. The encapsulant is singulated through the first insulating layer and saw street to separate the semiconductor die. A channel or net pattern can be formed in the first insulating layer on opposing sides of the saw street, or the first insulating layer covers the entire saw street and molding area around the semiconductor die.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: November 4, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Kang Chen, Jianmin Fang, Xia Feng, Xusheng Bao
  • Publication number: 20140239495
    Abstract: A semiconductor device is made by forming a first conductive layer over a carrier. The first conductive layer has a first area electrically isolated from a second area of the first conductive layer. A conductive pillar is formed over the first area of the first conductive layer. A semiconductor die or component is mounted to the second area of the first conductive layer. A first encapsulant is deposited over the semiconductor die and around the conductive pillar. A first interconnect structure is formed over the first encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The carrier is removed. A portion of the first conductive layer is removed. The remaining portion of the first conductive layer includes an interconnect line and UBM pad. A second interconnect structure is formed over a remaining portion of the first conductive layer is removed.
    Type: Application
    Filed: May 1, 2014
    Publication date: August 28, 2014
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Xusheng Bao, Kang Chen, Jianmin Fang
  • Patent number: 8796846
    Abstract: A semiconductor device is made by forming a first conductive layer over a carrier. The first conductive layer has a first area electrically isolated from a second area of the first conductive layer. A conductive pillar is formed over the first area of the first conductive layer. A semiconductor die or component is mounted to the second area of the first conductive layer. A first encapsulant is deposited over the semiconductor die and around the conductive pillar. A first interconnect structure is formed over the first encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The carrier is removed. A portion of the first conductive layer is removed. The remaining portion of the first conductive layer includes an interconnect line and UBM pad. A second interconnect structure is formed over a remaining portion of the first conductive layer is removed.
    Type: Grant
    Filed: October 2, 2009
    Date of Patent: August 5, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Xusheng Bao, Kang Chen, Jianmin Fang
  • Patent number: 8766426
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a carrier; mounting an integrated circuit device having component connectors directly on the carrier; placing a restraint structure over the integrated circuit device for controlling warpage of the integrated circuit device during bonding of the component connectors to the carrier causing some of the component connectors to separate from the carrier; and bonding all of the component connectors to the carrier.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: July 1, 2014
    Assignee: STATS ChipPac Ltd.
    Inventors: Hin Hwa Goh, Xusheng Bao, Yung Kuan Hsiao, Kang Chen, Rui Huang
  • Publication number: 20130140691
    Abstract: A semiconductor device has a semiconductor wafer with a first conductive layer formed over a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and first conductive layer. A second conductive layer is formed over the first insulating layer and first conductive layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A plurality of openings is formed in the second insulating layer in a bump formation area of the semiconductor wafer to expose the second conductive layer and reduce adverse effects of electro-migration. The openings are separated by portions of the second insulating layer. A UBM layer is formed over the openings in the second insulating layer in the bump formation area electrically connected to the second conductive layer. A bump is formed over the UBM layer.
    Type: Application
    Filed: December 6, 2011
    Publication date: June 6, 2013
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Xusheng Bao, Ma Phoo Pwint Hlaing, Jian Zuo
  • Patent number: 8455991
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit device having chip interconnects; applying an attachment layer directly on the integrated circuit device; attaching a device stiffener to the integrated circuit device with the attachment layer; attaching a chip carrier to the chip interconnects with the device stiffener attached to the integrated circuit device for controlling warpage of the integrated circuit device to prevent the warpage from causing some of the chip interconnects to separate from the chip carrier during attachment of the chip interconnects to the chip carrier; and applying an underfill between the chip carrier and the integrated circuit device for controlling connectivity of all the chip interconnects to the chip carrier.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: June 4, 2013
    Assignee: STATS ChipPAC Ltd.
    Inventors: Yung Kuan Hsiao, Xusheng Bao, Kang Chen, Hin Hwa Goh, Rui Huang