Patents by Inventor Ya Chen

Ya Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190088561
    Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device with a cell-like top layout, as well as a method for forming the IC. In some embodiments, the IC comprises a semiconductor substrate and the floating gate test device. The floating gate test device is on the semiconductor substrate, and comprises a floating gate electrode and a control gate electrode overlying the floating gate electrode. The floating gate electrode and the control gate electrode partially define an array of islands, and further partially define a plurality of bridges interconnecting the islands. The islands and the bridges define the cell-like top layout and may, for example, prevent process-induced damage to the floating gate test device.
    Type: Application
    Filed: April 25, 2018
    Publication date: March 21, 2019
    Inventors: Meng-Han Lin, Chih-Ren Hsieh, Ya-Chen Kao, Chen-Chin Liu, Chih-Pin Huang
  • Publication number: 20190046826
    Abstract: A liquid buoyancy muscle training device includes a liquid receiving tank receiving and holding liquid therein. A buoyantly submergible member is buoyantly submergible in the liquid contained in the liquid receiving tank and includes a regulation chamber formed therein. A bottom pulley is mounted inside the liquid receiving tank. A rope is connected to the buoyantly submergible member and wrapped around the bottom pulley and extends upward to project outside the liquid receiving tank. A liquid regulation tank is connected through a liquid supply tube to the regulation chamber to allow liquid to flow therebetween. A gas supplier is connected through a gas supply tube to the regulation chamber to selectively supply gas into the regulation chamber to change a ratio between liquid and gas inside the regulation chamber so as to change buoyance applied to the buoyantly submergible member by the liquid contained in the liquid receiving tank.
    Type: Application
    Filed: August 9, 2017
    Publication date: February 14, 2019
    Inventors: Chiang Liu, Ya-Chen Liu, Wei-Han Chen, Wen-Hsuan Pan
  • Patent number: 10182740
    Abstract: The present disclosure provides apparatuses and computer readable media for measuring sub-epidermal moisture in patients to determine damaged tissue for clinical intervention. The present disclosure also provides methods for determining damaged tissue.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: January 22, 2019
    Assignee: Bruin Biometrics, LLC
    Inventors: Ya-Chen Tonar, Shannon Rhodes, Marta Clendenin, Martin Burns, Kindah Jaradeh
  • Patent number: 10178961
    Abstract: The present disclosure provides apparatuses and computer readable media for measuring sub-epidermal moisture in patients to determine damaged tissue for clinical intervention. The present disclosure also provides methods for determining damaged tissue.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: January 15, 2019
    Assignee: Bruin Biometrics, LLC
    Inventors: Ya-Chen Tonar, Shannon Rhodes, Marta Clendenin, Martin Burns, Kindah Jaradeh
  • Publication number: 20180372928
    Abstract: The present invention provides a display device including a display panel and a haze layer. The display panel includes a plurality of pixels and a color determining surface. The orthogonal projection of each of the plurality of pixels onto the color determining surface forms a plurality of adjacent pixel ranges. The haze layer is disposed on a side of the color determining surface and has a haze surface facing away from the color determining surface. The haze layer has a scattering coefficient ranging from ?1.4 to 0. The haze surface includes a first location corresponding to the center of the first pixel range, and a second location corresponding to a location away from the first edge towards the second pixel range wherein the distance therebetween ranges from 87 ?m to 174 ?m.
    Type: Application
    Filed: June 15, 2018
    Publication date: December 27, 2018
    Inventors: Wang-Shuo Kao, Yu-Han Chiang, Ya-Chen Kao, Kai-Chieh Chang, Shang-Chiang Lin
  • Patent number: 10164659
    Abstract: Concepts and schemes pertaining to quasi-cyclic-low-density parity-check (QC-LDPC) coding are described. A processor of an apparatus may generate a QC-LDPC code having a plurality of codebooks embedded therein. The processor may select a codebook from the plurality of codebooks. The processor may also encode data using the selected codebook. Alternatively or additionally, the processor may generate the QC-LDPC code including at least one quasi-row orthogonal layer. Alternatively or additionally, the processor may generate the QC-LDPC code including a base matrix a portion of which forming a kernel matrix that corresponds to a code rate of at least a threshold value.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: December 25, 2018
    Assignee: MEDIATEK INC.
    Inventors: Mao-Ching Chiu, Chong-You Lee, Cheng-Yi Hsu, Timothy Perrin Fisher-Jeffes, Yen-Shuo Chang, Wei-Jen Chen, Ju-Ya Chen
  • Publication number: 20180367202
    Abstract: Techniques and examples pertaining to codeword mapping in New Radio (NR) and interleaver design for NR are described. A processor of an apparatus receives, via a transceiver of the apparatus, a Physical Downlink Shared Channel (PDSCH) transmission from a network node of a wireless network. The processor maps one or more codeblocks of a codeword in the PDSCH transmission to a spatial layer group which is a subset of a plurality of spatial layers. The processor also performs receive processing for one or more codeblocks in the PDSCH transmission including by performing de-interleaving on a result from a channel interleaver or from an intra-codeblock interleaver that performs pseudo-random interleaving on systematic bits and parity bits of the one or more codeblocks and channel decoding. The processor transmits, via the transceiver, to the network node a feedback concerning the one or more codeblock and reporting a result of the channel estimation.
    Type: Application
    Filed: June 16, 2018
    Publication date: December 20, 2018
    Inventors: Weidong Yang, Tzu-Han Chou, Ju-Ya Chen, Lung-Sheng Tsai
  • Publication number: 20180350877
    Abstract: Methods for forming a magneto-resistive memory device and a capacitor in an interconnect structure are disclosed herein. An exemplary method includes forming a first level interconnect metal layer and a second level interconnect metal layer of an interconnect structure. The method further includes simultaneously forming a first plurality of layers in a first region of the interconnect structure and a second plurality of layers in a second region of the interconnect structure, wherein the first plurality of layers and the second plurality of layers are disposed between the first level interconnect metal layer and the second level interconnect metal layer. The first plurality of layers is configured as a magneto-resistive memory device. The second plurality of layers is configured as the capacitor. The magneto-resistive memory device and the capacitor are each coupled to the first level interconnect metal layer and the second level interconnect metal layer.
    Type: Application
    Filed: July 25, 2018
    Publication date: December 6, 2018
    Inventors: Chung-Cheng Chou, Ya-Chen Kao, Tien-Wei Chiang
  • Publication number: 20180342529
    Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a split gate stack having a main gate and a select gate and forming a logic gate stack having a logic gate over a semiconductor substrate. The main gate and the logic gate is respectively replaced with a metal memory gate and a metal logic gate, in which the main gate and the logic gate are replaced simultaneously.
    Type: Application
    Filed: August 6, 2018
    Publication date: November 29, 2018
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Harry-Hak-Lay CHUANG, Wei-Cheng WU, Ya-Chen KAO
  • Patent number: 10138540
    Abstract: An infiltration device comprises a heating room, a rotary tray, a rotary bracket, a material box, an elevating mechanism and a transmission device, wherein the heating room has an annular groove, and the rotary tray is arranged below an opening end at a lower end of the heating room; the rotary bracket is installed on the rotary tray; the material box is arranged on the rotary bracket; the rotary tray and the material box can move upward and downward under the action of the elevating mechanism; the rotary bracket can spin in the annular groove and revolve around a central axis of the rotary tray under the action of the transmission device. The infiltration method provided by the invention comprises the steps of charging, vacuum-pumping, high temperature infiltrating, cooling, discharging, etc.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: November 27, 2018
    Assignee: Tianhe (Baotou) Advanced Tech Magnet Co., Ltd.
    Inventors: Juchang Miao, Yong Zhai, Jianxin Ma, Enfeng Gao, Yanling Song, Shulin Diao, Yi Dong, Haibo Yi, Shujie Wu, Yi Yuan, Ya Chen, Wenjie Yuan
  • Publication number: 20180331784
    Abstract: A processor of an apparatus selects a codebook from a plurality of codebooks embedded in a quasi-cyclic-low-density parity-check (QC-LDPC) code. The processor stores the selected codebook in a memory associated with the processor. The processor also encodes data using the selected codebook to generate a plurality of modulation symbols of the data. The processor further controls a transmitter of the apparatus to multiplex, convert, filter, amplify and radiate the modulation symbols as electromagnetic waves through one or more antennas of the apparatus. In selecting the codebook from the plurality of codebooks embedded in the QC-LDPC code, the processor selects the codebook according to one or more rules such that a small codebook requiring a shorter amount of processing latency for the encoding is selected for the encoding unless a larger codebook corresponding to a larger amount of processing latency for the encoding is necessary for the encoding.
    Type: Application
    Filed: May 31, 2018
    Publication date: November 15, 2018
    Inventors: Mao-Ching Chiu, Chong-You Lee, Timothy Perrin Fisher-Jeffes, Cheng-Yi Hsu, Yen-Shuo Chang, Wei-Jen Chen, Ju-Ya Chen
  • Publication number: 20180331695
    Abstract: A processor of an apparatus establishes a wireless communication link with at least one other apparatus via a transceiver of the apparatus. The processor wirelessly communicates with the other apparatus via the wireless communication link by: selecting a first shift-coefficient table from a plurality of shift-coefficient tables; generating a QC-LDPC code using a base matrix and at least a portion of the first shift-coefficient table; selecting a codebook from a plurality of codebooks embedded in the QC-LDPC code; storing the selected codebook in a memory associated with the processor; encoding data using the selected codebook to generate a plurality of modulation symbols of the data; and controlling the transceiver to multiplex, convert, filter, amplify and radiate the modulation symbols as electromagnetic waves through one or more antennas of the apparatus to transmit the modulation symbols of the data to the other apparatus via the wireless communication link.
    Type: Application
    Filed: June 28, 2018
    Publication date: November 15, 2018
    Inventors: Timothy Perrin Fisher-Jeffes, Chong-You Lee, Mao-Ching Chiu, Wei-Jen Chen, Ju-Ya Chen
  • Publication number: 20180331698
    Abstract: A processor of an apparatus establishes a wireless communication link with at least one other apparatus via a transceiver of the apparatus. The processor wirelessly communicates with the other apparatus via the wireless communication link by: selecting a first shift-coefficient table from a plurality of shift-coefficient tables; generating a QC-LDPC code using a base matrix and at least a portion of the first shift-coefficient table; selecting a codebook from a plurality of codebooks embedded in the QC-LDPC code; storing the selected codebook in a memory associated with the processor; encoding data using the selected codebook to generate a plurality of modulation symbols of the data; and controlling the transceiver to multiplex, convert, filter, amplify and radiate the modulation symbols as electromagnetic waves through one or more antennas of the apparatus to transmit the modulation symbols of the data to the other apparatus via the wireless communication link.
    Type: Application
    Filed: June 27, 2018
    Publication date: November 15, 2018
    Inventors: Chong-You Lee, Timothy Perrin Fisher-Jeffes, Mao-Ching Chiu, Wei-Jen Chen, Ju-Ya Chen
  • Publication number: 20180323801
    Abstract: An apparatus determines a code block size (CBS) of information bits contained in a codeword of low-density parity check (LDPC) coding. The apparatus compares the CBS with at least one threshold, determines, based on a result of the comparison, a Kb number and determines a Kp number based on a code rate and the Kb number. The apparatus generates a parity check matrix. An information portion of the parity check matrix is a first matrix formed by M number of second square matrices. M is equal to Kp multiplied by Kb. A total number of columns in the Kb number of second square matrices is equal to a total number of bits of the CBS. One or more matrices of the M number of second square matrices are circular permutation matrices. The apparatus operates an LDPC encoder or an LDPC decoder based on the parity check matrix.
    Type: Application
    Filed: May 4, 2018
    Publication date: November 8, 2018
    Inventors: Cheng-Yi HSU, Chong-You LEE, Wei Jen CHEN, Maoching CHIU, Timothy Perrin FISHER-JEFFES, Ju-Ya CHEN, Yen Shuo CHANG
  • Patent number: 10109401
    Abstract: The present invention provides a method for improving coercive force of magnets, this method comprises steps as follows: S2) coating step: coating a coating material on the surface of a magnet and drying it; and S3) infiltrating step: heat treating the magnet obtained from the coating step S2). The coating material comprises (1) metal calcium particles and (2) particles of a material containing a rare earth element; the rare earth element is at least one selected from Praseodymium, Neodymium, Gadolinium, Terbium, Dysprosium, Holmium, Erbium, Thulium, Ytterbium and Lutetium. The method of the present invention can significantly increase coercive force of a permanent magnet material, while remanence and magnetic energy product hardly decrease. In addition, the method of the present invention can significantly decrease the amount of a rare earth element, and accordingly, decrease the production cost.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: October 23, 2018
    Assignee: Tianhe (Baotou) Advanced Tech Magnet Co., Ltd.
    Inventors: Shujie Wu, Yi Dong, Shulin Diao, Haibo Yi, Yichuan Wang, Zhanjiang Hu, Juchang Miao, Yi Yuan, Ya Chen, Wenjie Yuan
  • Publication number: 20180288891
    Abstract: A hinge and an electronic device using the same are disclosed. The hinge includes a fixing member, a shaft member, and a spring member. The fixing member includes a pivoting portion and a fixing portion. The pivoting portion and the fixing portion are respectively fixed to opposite ends of the fixing member. The shaft member is pivotably connected to the pivoting portion. The spring member includes a spring body, a first end, and a second end. The spring body is between the first end and the second end. The first end is fixed to the shaft member. The second end is fixed to the fixing portion. When the shaft member rotates, the shaft member drives the spring body to twist via the first end.
    Type: Application
    Filed: March 31, 2017
    Publication date: October 4, 2018
    Inventors: Ting-Hsien WANG, Ya-Chen TSENG, Po-Hua CHU, Wei-Ting KUO, Chun-Chi SU, Tsung-Yu YANG
  • Publication number: 20180278267
    Abstract: Aspects of the disclosure provide an apparatus and a method for error correction based on a matrix. The apparatus includes memory and processing circuitry. The memory is configured to store the matrix associated with a set of parity bits. The matrix having rows and columns includes elements having values corresponding to either a first state or a second state. The matrix also includes a row having two elements with values corresponding to the first state. One of the two elements is a parity element corresponding to a parity bit associated with the row. Further, other elements in a same column as the parity element have values corresponding to the second state. The processing circuitry is configured to implement error correction based on the matrix. In another embodiment, the processing circuitry is configured to encode a data unit by generating the set of parity bits from the data unit based on the matrix and to form a codeword that includes the data unit and the set of parity bits.
    Type: Application
    Filed: March 9, 2018
    Publication date: September 27, 2018
    Applicant: MEDIATEK INC.
    Inventors: Chong-You LEE, Timothy Perrin Fisher-Jeffes, Maoching Chiu, Wei Jen Chen, Cheng-Yi Hsu, Ju-Ya Chen, Yen Shuo Chang
  • Patent number: 10068773
    Abstract: An integrated circuit structure includes a plurality of flash memory cells forming a memory array, wherein each of the plurality of flash memory cells includes a select gate and a memory gate. A select gate electrode includes a first portion including polysilicon, wherein the first portion forms select gates of a column of the memory array, and a second portion electrically connected to the first portion, wherein the second portion includes a metal. A memory gate electrode has a portion forming memory gates of the column of the memory array.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: September 4, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Wei-Cheng Wu, Ya-Chen Kao, Chin-Yi Huang
  • Patent number: 10050050
    Abstract: A semiconductor device includes a substrate, at least one split gate memory device, and at least one logic device. The split gate memory device is disposed on the substrate. The logic device is disposed on the substrate. A select gate or a main gate of the split gate memory device and a logic gate of the logic device are both made of metal, and the other gate of the split gate memory device is made of nonmetal.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: August 14, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Harry Hak-Lay Chuang, Wei-Cheng Wu, Ya-Chen Kao
  • Patent number: 10050047
    Abstract: The present disclosure relates a method for manufacturing an integrated circuit. In some embodiments, a semiconductor substrate is provided and made up of a memory array region and a boundary region surrounding the memory array region. A hard mask layer is formed over the memory array region and the boundary region. The hard mask layer is patterned to form a boundary hard mask having one or more slots to expose some portions of the boundary region while the remaining regions of the boundary region are covered by the boundary hard mask. A floating gate layer is formed within the memory array region and extending over the hard mask layer. Then, a planarization is performed to reduce a height of the floating gate layer and form a plurality of floating gates.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Harry-Hak-Lay Chuang, Chin-Yi Huang, Ya-Chen Kao