Abstract: A method for decoding a current block of a picture is disclosed. First, at least one illumination compensation parameter for the current block is decoded responsive to a comparison of a parameter of the current block with a value. Then, an accessed motion compensation reference block is compensated in illumination responsive to the at least one illumination compensation parameter. Finally, the current block is reconstructed from the illumination and motion compensated reference block.

Abstract: A gear drive mechanism includes: a motor; a transmission member provided on a rotating shaft of the motor; a support plate that has a support plate surface, and to which the motor is attached to cause the transmission member to intersect with the support plate surface in a diagonal direction; a first gear that has first helical teeth that mesh with the transmission member and is rotatably attached to the support plate, the first gear rotating in a first direction by rotation of the motor; and a second gear that has second helical teeth and is rotatably attached to the support plate, the second gear rotating in synchronization with rotation of the first gear in a second direction opposite to the first direction.

Abstract: A method of hybrid automatic repeat request (HARQ) feedback can include receiving data transmitted from a transmission (Tx) user equipment (UE) or a base station (BS) over a channel at a reception (Rx) UE, selecting an acknowledgement/negative acknowledgement (A/N) resource from a set of A/N resources for a HARQ feedback of the data based on a channel condition of the channel or a geographical location of the Rx UE, and transmitting the HARQ feedback with the selected A/N resource.

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device with a cell-like top layout, as well as a method for forming the IC. In some embodiments, the IC comprises a semiconductor substrate and the floating gate test device. The floating gate test device is on the semiconductor substrate, and comprises a floating gate electrode and a control gate electrode overlying the floating gate electrode. The floating gate electrode and the control gate electrode partially define an array of islands, and further partially define a plurality of bridges interconnecting the islands. The islands and the bridges define the cell-like top layout and may, for example, prevent process-induced damage to the floating gate test device.

Abstract: A method and an apparatus for coding a video are disclosed. At least one transform subblock in a block of a picture of the video is determined (1600) depending on a shape of the block and the block is coded (1630) based at least on the determined transform subblock. Corresponding decoding method and apparatus are disclosed.

Abstract: A video codec can involve processing video information based on a motion model involving a coding unit including a plurality of sub-blocks, such as an affine motion model, to produce motion compensation information, obtaining a local illumination compensation model, and encoding or decoding the video information based on the motion compensation information and the local illumination compensation model.

Abstract: A storage module of distributed flow battery is provided. An electrochemical reaction is processed with the positive and negative electrolytes to produce and/or discharge direct current and further output the positive and negative electrolytes after the reaction. The module comprises two end plates; two frames disposed between the two end plates; two current collectors disposed between the two frames; two complex cast polar plates disposed between the two current collectors; two electrodes disposed between the two complex cast polar plates; a membrane disposed between the two electrodes; and three gaskets. Therein, two of the gaskets are set to sandwich and enclose one of the two complex cast polar plates; and the other one of the gaskets is set between the other one of the two complex cast polar plates and an adjacent one of the current collectors.

Abstract: A memory device includes a semiconductor substrate, a select gate stack, a main gate, a charge trapping layer, and a spacer. The a select gate stack is over the semiconductor substrate. The main gate is over the semiconductor substrate. The charge trapping layer has a first portion between the main gate and the semiconductor substrate. The spacer is on a sidewall of the main gate. At least a portion of the main gate is between the spacer and the select gate stack, and a lowermost surface of the spacer is above a lowermost surface of the main gate.

Abstract: A method of detecting a biological sample includes the following steps. A magnetic sensor chip is provided, wherein the magnetic sensor chip includes a substrate and a magnetic sensing layer located on the substrate. Probes are connected to the magnetic sensor chip. A sample solution containing biological samples labeled with a first marker is provided on the magnetic sensor chip, so that the biological samples labeled with the first marker are hybridized with the probes. Magnetic beads labeled with a second marker are provided on the magnetic sensor chip, so that the magnetic beads labeled with the second marker are bound onto the biological samples labeled with the first marker. A signal sensed by the magnetic sensing layer is detected by a magnetic sensor.

Abstract: Different implementations are described for determining one or more illumination compensation parameters for a current block being encoded by a video encoder or decoded by a video decoder. A plurality of motion vectors for a current block being encoded in a picture are determined. One or more illumination compensation parameters for each of the plurality of motion vectors are determined and encoded or decoded. The current block is then encoded or decoded using the plurality of motion vectors and the one or more illumination compensation parameters for each of the plurality of motion vectors. In one embodiment, a flag is used to signal the use or not of the illumination compensation. In another embodiment, the illumination compensation flag is not encoded or decoded if illumination compensation is not used.

Abstract: The present disclosure relates to an integrated circuit that includes a semiconductor substrate having a periphery region and memory cell region separated by a boundary region. A pair of split gate flash memory cells are disposed on the memory cell region and include a first select gate and a first memory gate. A first gate electrode is disposed over a first gate dielectric layer on the periphery region. A second gate electrode is disposed over a second gate dielectric layer on the periphery region at a position between the boundary region and the first gate electrode. The second dielectric layer is thicker than the first gate dielectric layer. The first select gate and the first memory gate have upper surfaces that are co-planar or level with the upper surface of the second gate electrode.

Abstract: An automatic sewage regulation system and a regulating method are provided. The automatic sewage regulation system is disposed between preset sewage sources and a preset sewage treatment apparatus and includes an equalization tank and an automatic sewage regulating device. The automatic sewage regulating device includes sensing modules for sensing and transmitting water quality sensing values of sewage in the preset sewage sources to a control module which outputs regulating signals to water flow regulators, so that the water flow regulators can regulate flowing volumes of the sewage of the preset sewage sources according to the regulating signal, to keep a water quality sensing value of the sewage in the equalization tank within a preset range, thereby preventing the equalization tank from converging sewage having excessively-high or excessively-low water quality sensing value. As a result, burden of the preset sewage treatment apparatus can be reduced.

Abstract: The disclosure discloses a method for preparing a permanent magnet material. In this method, an ionic liquid electroplating process is used to electroplate a heavy rare earth metal onto a surface of a sintered magnet to form a magnet with a coating, wherein the sintered magnet has a thickness of 10 mm or less in at least one direction; in the ionic liquid electroplating process, an electroplating solution comprises an ionic liquid, a heavy rare earth salt, a group VIII metal salt, an alkali metal salt and an additive, an anode is a heavy rare earth metal or a heavy rare earth alloy, a cathode is the sintered magnet, an electroplating temperature is 20-50° C., an electroplating time is 15-80 min. The preparation method of the disclosure can improve an intrinsic coercive force of the magnet with low cost and high production efficiency. A utilization rate of heavy rare earth is high.

Abstract: A device assembly structure includes a first device and at least one second device. The first device has a first active surface and a first backside surface opposite to the first active surface, and includes a plurality of first electrical contacts disposed adjacent to the first active surface. The second device has a second active surface and a second backside surface opposite to the second active surface, and includes a plurality of second electrical contacts disposed adjacent to the second active surface. The second active surface of the second device faces the first active surface of the first device, the second electrical contacts of the second device are electrically connected to the first electrical contacts of the first device, and a thickness of the second device is less than or equal to one fifth of a thickness of the first device.

Abstract: A storage module of distributed flow battery is provided. An electrochemical reaction is processed with the positive and negative electrolytes to produce and/or discharge direct current and further output the positive and negative electrolytes after the reaction. The module comprises two end plates; two frames disposed between the two end plates; two current collectors disposed between the two frames; two complex cast polar plates disposed between the two current collectors; two electrodes disposed between the two complex cast polar plates; a membrane disposed between the two electrodes; and three gaskets. Therein, two of the gaskets are set to sandwich and enclose one of the two complex cast polar plates; and the other one of the gaskets is set between the other one of the two complex cast polar plates and an adjacent one of the current collectors.

Abstract: Methods for forming a magneto-resistive memory device and a capacitor in an interconnect structure are disclosed herein. An exemplary method includes forming a first level interconnect metal layer and a second level interconnect metal layer of an interconnect structure. The method further includes simultaneously forming a first plurality of layers in a first region of the interconnect structure and a second plurality of layers in a second region of the interconnect structure, wherein the first plurality of layers and the second plurality of layers are disposed between the first level interconnect metal layer and the second level interconnect metal layer. The first plurality of layers is configured as a magneto-resistive memory device. The second plurality of layers is configured as the capacitor. The magneto-resistive memory device and the capacitor are each coupled to the first level interconnect metal layer and the second level interconnect metal layer.

Abstract: The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a HKMG (high-? metal gate) integrated circuit which includes a high-voltage (HV) HKMG transistor. NVM devices (e.g., flash memory) are operated at high voltages for its read and write operations and hence a HV device is necessary for integrated circuits involving non-volatile embedded memory and HKMG logic circuits. Forming a HV HKMG circuit along with the HKMG periphery circuit reduces the need for additional boundaries between the HV transistor and rest of the periphery circuit. This method further helps reduce divot issue and reduce cell size.

Abstract: Concepts and schemes pertaining to location of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide a stream of encoded data. The processor also rate matches the encoded data to provide a rate-matched stream of encoded data. The processor further interleaving the rate-matched stream of encoded data. In rate matching the encoded data, the processor buffers the stream of encoded data in a circular buffer, with the circular buffer functioning as a rate matching block that rate matches the stream of encoded data. In interleaving the rate-matched stream of encoded data, the processor performs bit-level interleaving on the rate-matched stream of encoded data to provide a stream of interleaved data.

Abstract: A semiconductor device includes active gate structures and dummy gate electrodes. The active gate structures are above an active region of a substrate. The dummy gate electrodes are above the active region of the substrate. A number of the dummy gate electrodes is less than a number of the active gate structures. The active gate structures and the dummy gate electrodes have different materials, and a distance between adjacent one of the dummy gate electrodes and one of the active gate structures is substantially the same as a gate pitch of the active gate structures.

Abstract: Disclosed is a sintered body, a sintered permanent magnet and preparation methods. The sintered body comprises Nd2Fe14B crystal phase as a primary phase and a rare earth rich phase as a grain boundary phase and has a composition expressed by composition formula RaBbGacCudAleMfCogFebalance; R is one or more selected from rare earth elements, and R must comprise Nd; M is one or more selected from the group consisting of Zr, Ti, and Nb; a satisfies 13%?a?15.3%; b satisfies 5.4%?b?5.8%; c satisfies 0.05%?c?0.25%; d satisfies 0.08%?d?0.3%; e satisfies 0?e?1.2%; f satisfies 0.08%?f?0.2%; g satisfies 0.8%?g?2.5%; grains in Nd2Fe14B crystal phase have average size L of 4-8 ?m, grain boundary phases have average thickness t with unit of ?m; the relation of t and L is: ?=t/L; and ? is defined as 0.009???0.012. The present disclosure improves diffusion efficiency of heavy rare earth elements RH.