Patents by Inventor Ya-Huei Tsai

Ya-Huei Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210225933
    Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region and a gate pattern extending from the first active region to the second active region, in which the gate pattern includes a H-shape according to a top view. Preferably, the gate pattern includes a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, and a third gate pattern connecting the first gate pattern and the second gate pattern along a second direction.
    Type: Application
    Filed: February 16, 2020
    Publication date: July 22, 2021
    Inventors: Ya-Huei Tsai, Rai-Min Huang, Yu-Ping Wang, Hung-Yueh Chen
  • Publication number: 20210151664
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) stack on a substrate; forming a top electrode on the MTJ stack; performing a first patterning process to remove the MTJ stack along a first direction; and performing a second patterning process to remove the MTJ stack along a second direction to form MTJs on the substrate.
    Type: Application
    Filed: December 4, 2019
    Publication date: May 20, 2021
    Inventors: Jia-Rong Wu, Rai-Min Huang, Ya-Huei Tsai, I-Fan Chang, Yu-Ping Wang
  • Publication number: 20210135092
    Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate and a dummy MTJ between the first MTJ and the second MTJ, in which a bottom surface of the dummy MTJ is not connected to any metal. Preferably, the semiconductor device further includes a first metal interconnection under the first MTJ, a second metal interconnection under the second MTJ, and a first inter-metal dielectric (IMD) layer around the first metal interconnection and the second metal interconnection and directly under the dummy MTJ.
    Type: Application
    Filed: November 27, 2019
    Publication date: May 6, 2021
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Jing-Yin Jhang, Hung-Yueh Chen, Yu-Ping Wang, Jia-Rong Wu, Rai-Min Huang, Ya-Huei Tsai, I-Fan Chang
  • Patent number: 10944048
    Abstract: A semiconductor device includes a substrate, an array of magnetic tunnel junctions (MTJs), an array of first dummy MTJs, and an array of second dummy MTJs. The substrate includes an array region defined thereon, and the array region includes at least an outermost corner. The array of MTJs is disposed in the array region. The array of the first dummy MTJs is disposed along the outermost corner of the array region. The array of the second dummy MTJs is disposed around the array region and the array of first dummy MTJs.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: March 9, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ya-Huei Tsai, Rai-Min Huang
  • Patent number: 10930704
    Abstract: A magnetic memory cell includes a substrate, a transistor, a first dielectric layer disposed on the substrate, a landing pad in the first dielectric layer, a second dielectric layer covering the first dielectric layer and the landing pad, a memory stack in the second dielectric layer, and a source line in the first dielectric layer. The first dielectric layer covers the transistor. The landing pad is situated in a first horizontal plane and is coupled to a drain region of the transistor. The memory stack has a bottom electrode connected to the landing pad and a top electrode electrically connected to a bit line. The source line is situated in a second horizontal plane and is connected to a source region of the transistor. The second horizontal plane and the first horizontal plane are not coplanar.
    Type: Grant
    Filed: March 8, 2020
    Date of Patent: February 23, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Rai-Min Huang, Hung-Yueh Chen, Ya-Huei Tsai, Yu-Ping Wang
  • Publication number: 20210028353
    Abstract: A semiconductor device includes a substrate, an array of magnetic tunnel junctions (MTJs), an array of first dummy MTJs, and an array of second dummy MTJs. The substrate includes an array region defined thereon, and the array region includes at least an outermost corner. The array of MTJs is disposed in the array region. The array of the first dummy MTJs is disposed along the outermost corner of the array region. The array of the second dummy MTJs is disposed around the array region and the array of first dummy MTJs.
    Type: Application
    Filed: August 28, 2019
    Publication date: January 28, 2021
    Inventors: Ya-Huei Tsai, Rai-Min Huang
  • Publication number: 20210020694
    Abstract: A magnetic memory cell includes a substrate, a transistor, a first dielectric layer disposed on the substrate, a landing pad in the first dielectric layer, a second dielectric layer covering the first dielectric layer and the landing pad, a memory stack in the second dielectric layer, and a source line in the first dielectric layer. The first dielectric layer covers the transistor. The landing pad is situated in a first horizontal plane and is coupled to a drain region of the transistor. The memory stack has a bottom electrode connected to the landing pad and a top electrode electrically connected to a bit line. The source line is situated in a second horizontal plane and is connected to a source region of the transistor. The second horizontal plane and the first horizontal plane are not coplanar.
    Type: Application
    Filed: March 8, 2020
    Publication date: January 21, 2021
    Inventors: Rai-Min Huang, Hung-Yueh Chen, Ya-Huei Tsai, Yu-Ping Wang
  • Patent number: 10714466
    Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes: a first magnetic tunneling junction (MTJ) pattern on a substrate; a second MTJ pattern adjacent to the first MTJ pattern; and a first metal interconnection pattern between the first MTJ pattern and the second MTJ pattern, wherein the first MTJ pattern, the first metal interconnection pattern, and the second MTJ pattern comprise a staggered arrangement.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: July 14, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Liang Chu, Chih-Hsien Tang, Yu-Ruei Chen, Ya-Huei Tsai, Rai-Min Huang, Chueh-Fei Tai
  • Publication number: 20200212030
    Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes: a first magnetic tunneling junction (MTJ) pattern on a substrate; a second MTJ pattern adjacent to the first MTJ pattern; and a first metal interconnection pattern between the first MTJ pattern and the second MTJ pattern, wherein the first MTJ pattern, the first metal interconnection pattern, and the second MTJ pattern comprise a staggered arrangement.
    Type: Application
    Filed: January 23, 2019
    Publication date: July 2, 2020
    Inventors: Chung-Liang Chu, Chih-Hsien Tang, Yu-Ruei Chen, Ya-Huei Tsai, Rai-Min Huang, Chueh-Fei Tai
  • Patent number: 10622407
    Abstract: A magnetic memory cell includes a substrate having a memory region, a transistor within the memory region, a first dielectric layer disposed on the substrate, a landing pad in the first dielectric layer, a second dielectric layer covering the first dielectric layer and the landing pad, a cylindrical memory stack in the second dielectric layer, and a source line in the first dielectric layer. The first dielectric layer covers the memory region and the transistor. The landing pad is situated in a first horizontal plane and is coupled to a drain region of the transistor. The cylindrical memory stack has a bottom electrode connected to the landing pad and a top electrode electrically connected to a bit line. The source line is situated in a second horizontal plane and is connected to a source region of the transistor. The second horizontal plane is lower than the first horizontal plane.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: April 14, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Rai-Min Huang, Hung-Yueh Chen, Ya-Huei Tsai, Yu-Ping Wang
  • Patent number: 10290723
    Abstract: A semiconductor device includes a substrate and a gate structure on the substrate, in which the gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, the middle portion being a nitrogen rich portion, the top portion and the bottom portion being titanium rich portions, and the top portion, the middle portion, and the bottom portion are of same material composition.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: May 14, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Tsen Lu, Chien-Ming Lai, Lu-Sheng Chou, Ya-Huei Tsai, Ching-Hsiang Chiu, Yu-Tung Hsiao, Chen-Ming Huang, Kun-Ju Li, Yu-Ping Wang
  • Publication number: 20180269308
    Abstract: A semiconductor device includes a substrate and a gate structure on the substrate, in which the gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, the middle portion being a nitrogen rich portion, the top portion and the bottom portion being titanium rich portions, and the top portion, the middle portion, and the bottom portion are of same material composition.
    Type: Application
    Filed: May 17, 2018
    Publication date: September 20, 2018
    Inventors: Chun-Tsen Lu, Chien-Ming Lai, Lu-Sheng Chou, Ya-Huei Tsai, Ching-Hsiang Chiu, Yu-Tung Hsiao, Chen-Ming Huang, Kun-Ju Li, Yu-Ping Wang
  • Patent number: 10008581
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate and a gate structure on the substrate. The gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, in which the top portion being a nitrogen rich portion, and the middle portion and the bottom portion being titanium rich portions.
    Type: Grant
    Filed: August 30, 2015
    Date of Patent: June 26, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Tsen Lu, Chien-Ming Lai, Lu-Sheng Chou, Ya-Huei Tsai, Ching-Hsiang Chiu, Yu-Tung Hsiao, Chen-Ming Huang, Kun-Ju Li, Yu-Ping Wang
  • Patent number: 9721840
    Abstract: The present invention provides a complementary metal oxide semiconductor device, comprising a PMOS and an NMOS. The PMOS has a P type metal gate, which comprises a bottom barrier layer, a P work function metal (PWFM) layer, an N work function tuning (NWFT) layer, an N work function metal (NWFM) layer and a metal layer. The NMOS has an N type metal gate, which comprises the NWFT layer, the NWFM layer and the low-resistance layer. The present invention further provides a method of forming the same.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: August 1, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Ming Lai, Chien-Chung Huang, Yu-Ting Tseng, Ya-Huei Tsai, Yu-Ping Wang
  • Patent number: 9679898
    Abstract: A semiconductor device having metal gate includes a first metal gate structure and a second metal gate structure disposed in a first device region and in a second device region on a substrate respectively. The first metal gate structure includes a gate insulating layer, a first bottom barrier layer, a top barrier layer, and a metal layer disposed on the substrate in order, wherein the top barrier layer is directly in contact with the first bottom barrier layer. The second metal gate structure includes the gate insulating layer, a second bottom barrier layer, the top barrier layer, and the metal layer on the substrate in order, wherein the top barrier layer is directly in contact with the second bottom barrier layer. The first bottom barrier layer and the second bottom barrier layer have different impurity compositions.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: June 13, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Ming Lai, Ya-Huei Tsai
  • Publication number: 20170047330
    Abstract: A semiconductor device having metal gate includes a first metal gate structure and a second metal gate structure disposed in a first device region and in a second device region on a substrate respectively. The first metal gate structure includes a gate insulating layer, a first bottom barrier layer, a top barrier layer, and a metal layer disposed on the substrate in order, wherein the top barrier layer is directly in contact with the first bottom barrier layer. The second metal gate structure includes the gate insulating layer, a second bottom barrier layer, the top barrier layer, and the metal layer on the substrate in order, wherein the top barrier layer is directly in contact with the second bottom barrier layer. The first bottom barrier layer and the second bottom barrier layer have different impurity compositions.
    Type: Application
    Filed: November 1, 2016
    Publication date: February 16, 2017
    Inventors: Chien-Ming Lai, Ya-Huei Tsai
  • Publication number: 20170040435
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate and a gate structure on the substrate. The gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, in which the top portion being a nitrogen rich portion, and the middle portion and the bottom portion being titanium rich portions.
    Type: Application
    Filed: August 30, 2015
    Publication date: February 9, 2017
    Inventors: Chun-Tsen Lu, Chien-Ming Lai, Lu-Sheng Chou, Ya-Huei Tsai, Ching-Hsiang Chiu, Yu-Tung Hsiao, Chen-Ming Huang, Kun-Ju Li, Yu-Ping Wang
  • Patent number: 9524968
    Abstract: A fabrication method of semiconductor device having metal gate includes providing a substrate, successively forming a gate insulating layer and a bottom barrier layer on the surface of the substrate, forming a work function layer covering the bottom barrier layer, removing the work function layer, and forming a top barrier layer on the bottom barrier layer to be directly contact with the bottom barrier layer, and forming a metal layer on the top bottom barrier layer.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: December 20, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Ming Lai, Ya-Huei Tsai
  • Patent number: 9524967
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device include a substrate, and a first transistor, a second transistor and a third transistor all disposed on the substrate. The first transistor includes a first channel, and a first barrier layer and a first work function layer stacked with each other on the first channel. The second transistor includes a second channel, and a second barrier layer and a second work function layer stacked with each other. The third transistor includes a third channel and a third barrier layer and a third work function layer stacked with each other on the third channel, wherein the first barrier layer, the second barrier layer and the third barrier layer have different nitrogen ratio. The first, the second and the third transistors have different threshold voltages, respectively.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: December 20, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hao-Yeh Liu, Chien-Ming Lai, Yu-Ping Wang, Mon-Sen Lin, Ya-Huei Tsai, Ching-Hsiang Chiu
  • Publication number: 20160307805
    Abstract: The present invention provides a complementary metal oxide semiconductor device, comprising a PMOS and an NMOS. The PMOS has a P type metal gate, which comprises a bottom barrier layer, a P work function metal (PWFM) layer, an N work function tuning (NWFT) layer, an N work function metal (NWFM) layer and a metal layer. The NMOS has an N type metal gate, which comprises the NWFT layer, the NWFM layer and the low-resistance layer. The present invention further provides a method of forming the same.
    Type: Application
    Filed: June 28, 2016
    Publication date: October 20, 2016
    Inventors: Chien-Ming Lai, Chien-Chung Huang, Yu-Ting Tseng, Ya-Huei Tsai, Yu-Ping Wang