Patents by Inventor Ya-Jui Lee

Ya-Jui Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10714197
    Abstract: A memory device and a program verification method thereof are provided. The write verification method includes: reading a previous page to obtain first read data, writing input data to a current page, reading the previous page or the current page to obtain second read data, and analyzing at least one of the first read data and the second read data to determine whether to back up at least one of the first read data and the input data to a redundant block of the memory device.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: July 14, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Ya-Jui Lee, Kuan-Fu Chen
  • Patent number: 10665303
    Abstract: Methods, systems and apparatus for effectively erasing blocks with few programmed pages are provided. In one aspect, a system includes a memory and a controller coupled to the memory. The memory includes blocks each having pages. The controller is configured to determine whether a threshold page with a particular page number in a block of the memory is programmed, to erase the block according to a normal erase action in response to determining that the threshold page is programmed, and to erase the block according to a particular erasing action that is configured to erase the block deeper than the normal erase action in response to determining that the threshold page is not programmed. The particular erasing action can include pre-programming the block before erasing the block, decreasing an erase verify voltage before erasing the block, or adding one or more erasing pulses with a new erasing voltage.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: May 26, 2020
    Assignee: Macronix International Co., Ltd.
    Inventors: Ya-Jui Lee, Kuan-Fu Chen
  • Patent number: 10460808
    Abstract: Provided is an operation method for a memory device. The memory device includes a memory array having a plurality of word lines and a plurality of bit lines. The operation method for the memory device includes: applying a program voltage to at least one selected word line of the word lines; and during a high level of the program voltage, based on respective locations of a plurality of selected bit line, which are to be written into data 0, on the word lines, applying different plurality of bit line voltages to the selected bit line which are to be written into data 0.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: October 29, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Ya-Jui Lee, Kuan-Fu Chen
  • Publication number: 20190122735
    Abstract: Provided is an operation method for a memory device. The memory device includes a memory array having a plurality of word lines and a plurality of bit lines. The operation method for the memory device includes: applying a program voltage to at least one selected word line of the word lines; and during a high level of the program voltage, based on respective locations of a plurality of selected bit line, which are to be written into data 0, on the word lines, applying different plurality of bit line voltages to the selected bit line which are to be written into data 0.
    Type: Application
    Filed: October 25, 2017
    Publication date: April 25, 2019
    Inventors: Ya-Jui Lee, Kuan-Fu Chen
  • Patent number: 10262748
    Abstract: A non-volatile memory and a program method thereof are provided. The program method of the non-volatile memory includes: setting a first incremental value, and providing a plurality of first pulses of incrementally increasing voltages in sequence according to the first incremental value for performing a programming operation on a plurality of non-volatile memory cells during a first time period; and setting a second incremental value, and providing a plurality of second pulses of incrementally increasing voltages in sequence according to the second incremental value for performing a programming operation on the non-volatile memory cells during a second time period which is after the first time period, wherein the first incremental value is smaller than the second incremental value.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: April 16, 2019
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Ya-Jui Lee, Atsuhiro Suzuki
  • Patent number: 10026490
    Abstract: A memory device and a programming method thereof are provided, and the programming method of the memory device includes following steps. A memory cell grouping procedure is performed to divide a plurality of memory cells into a plurality of groups. After the memory cell grouping procedure is performed, a programming procedure is performed, and the programming procedure includes following steps. A first programming pulse, a second programming pulse and a verification pulse are provided to a word line. A first group is programmed by the first programming pulse, and a second group is programmed by the second programming pulse. Whether the first group and the second group respectively pass a verification operation is determined by the verification pulse.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: July 17, 2018
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Ya-Jui Lee, Kuan-Fu Chen
  • Publication number: 20180061503
    Abstract: A memory device and a programming method thereof are provided, and the programming method of the memory device includes following steps. A memory cell grouping procedure is performed to divide a plurality of memory cells into a plurality of groups. After the memory cell grouping procedure is performed, a programming procedure is performed, and the programming procedure includes following steps. A first programming pulse, a second programming pulse and a verification pulse are provided to a word line. A first group is programmed by the first programming pulse, and a second group is programmed by the second programming pulse. Whether the first group and the second group respectively pass a verification operation is determined by the verification pulse.
    Type: Application
    Filed: October 7, 2016
    Publication date: March 1, 2018
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Ya-Jui Lee, Kuan-Fu Chen
  • Patent number: 9779820
    Abstract: A non-volatile memory and a programming method thereof are provided. The programming method for the non-volatile memory includes: setting at least one first isolation cell between a first side cell and at least one first pass cell of an inhibited memory string; cutting off the at least one first isolation cell and providing a pre-boosting voltage to a word line of the first side cell and at a first time point; turning on the at least one first isolation cell at a second time point for transporting the pre-boosting potential to channels of the at least one first pass cell and a primary cell at a second time period; and providing a boosting voltage to word lines of the at least one first pass cell during a boosting time period.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: October 3, 2017
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Ya-Jui Lee, Kuan-Fu Chen
  • Patent number: 9613702
    Abstract: A memory device including multiple word lines, multiple bit lines and a memory cell array is provided. The word lines intersect the bit lines, and an included angle between the word lines and the bit lines is not a right angle. The memory cell array includes multiple memory cells respectively disposed at the intersections of the word lines and the bit lines. Each row of the memory cells is electrically connected to one of the word lines, and each column of the memory cells is electrically connected to one of the bit lines.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: April 4, 2017
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Ya-Jui Lee, Kuan-Fu Chen
  • Patent number: 9543001
    Abstract: First threshold voltages of one or more memory cells in a memory array are obtained. For each memory cell in the one or more memory cells, a target threshold voltage for the memory cell is identified. A number of programming shots to reach the target threshold voltage of the memory cell is determined based on the first threshold voltage of the memory cell. Respective number of programming shots, which are determined for the one or more memory cells, are applied to the one or more memory cells. Whether respective target threshold voltages for the one or more memory cells are reached is verified upon applying the respective number of programming shots to the one or more memory cells.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: January 10, 2017
    Assignee: Macronix International Co., Ltd.
    Inventors: Ya Jui Lee, Kuan Fu Chen
  • Patent number: 9530508
    Abstract: A memory device and a method for operating the same are provided. The memory device includes a substrate, a plurality of word lines, and a plurality of dummy word lines. The word lines and the dummy word lines are located on the substrate. At least one side of each dummy word line is adjacent to the word line. At least one word line and at least one dummy word line form a group. The method for operating the memory device includes the following. At least one group is selected, and the group is operated. A first operational voltage is applied to the word line of the group. A second operational voltage is applied to the dummy word line of the group.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: December 27, 2016
    Assignee: MACRONIX International Co., Ltd.
    Inventor: Ya-Jui Lee
  • Publication number: 20160307636
    Abstract: Methods and apparatuses are contemplated herein for enhancing the read performance and data retention of nonvolatile memory devices. In an example embodiment, a method is provided for controlling a nonvolatile memory device that includes a matrix of memory cells, wherein each memory cell in the matrix includes a programmable floating gate. The method includes programming a floating gate of a first memory cell of the nonvolatile memory device, and shifting a voltage of the floating gate of the first memory cell of the nonvolatile memory device by creating a coupling effect that impacts the floating gate of the first memory cell. In this regard, the method may include programming one or more nearby memory cells, in which case the coupling effect may comprise a floating gate coupling effect between the first memory cell and the one or more nearby memory cells.
    Type: Application
    Filed: April 17, 2015
    Publication date: October 20, 2016
    Inventors: Ya Jui Lee, Kuan Fu Chen
  • Patent number: 9437319
    Abstract: Provided are methods, devices, and/or the like for reducing the bit line interference when programming non-volatile memory. One method comprises providing a non-volatile memory device comprising a set of cells, each cell associated with a bit line; shooting a programming voltage across each cell; detecting a threshold voltage for each cell; identifying a fast subset of the set of cells and a slow subset of the set of cells based at least in part on the detected threshold voltage for each cell; and shooting the programming voltage until the threshold voltage for each cell is greater than a verify voltage. For each shot a fast bit line bias is applied to the bit line associated each cell of the fast subset and a slow bit line bias is applied to the bit line associated with each cell of the slow subset.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: September 6, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Atsuhiro Suzuki, Ya Jui Lee, Kuan Fu Chen, Chih-Wei Lee
  • Patent number: 9424926
    Abstract: A nonvolatile semiconductor device is provided that includes a substrate and a plurality of blocks forming a string. Each block is positioned on the substrate and includes a plurality of word lines disposed on the substrate. The string includes a single ground select line disposed at one side of the plurality of blocks, and a single string select line is disposed at another side of the plurality of blocks. In some embodiments, the word lines of the plurality of blocks define gaps separating each block of the string from neighboring blocks of the string. One or more dummy word lines may be disposed in each gap between blocks of the string. Corresponding methods of manufacturing the nonvolatile semiconductor device and manipulating the nonvolatile semiconductor device are provided.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: August 23, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Ya Jui Lee, Kuan Fu Chen
  • Publication number: 20160155510
    Abstract: A memory device and a method for operating the same are provided. The memory device includes a substrate, a plurality of word lines, and a plurality of dummy word lines. The word lines and the dummy word lines are located on the substrate. At least one side of each dummy word line is adjacent to the word line. At least one word line and at least one dummy word line form a group. The method for operating the memory device includes the following. At least one group is selected, and the group is operated. A first operational voltage is applied to the word line of the group. A second operational voltage is applied to the dummy word line of the group.
    Type: Application
    Filed: December 2, 2014
    Publication date: June 2, 2016
    Inventor: Ya-Jui Lee
  • Publication number: 20160155508
    Abstract: A nonvolatile semiconductor device is provided that includes a substrate and a plurality of blocks forming a string. Each block is positioned on the substrate and includes a plurality of word lines disposed on the substrate. The string includes a single ground select line disposed at one side of the plurality of blocks, and a single string select line is disposed at another side of the plurality of blocks. In some embodiments, the word lines of the plurality of blocks define gaps separating each block of the string from neighboring blocks of the string. One or more dummy word lines may be disposed in each gap between blocks of the string. Corresponding methods of manufacturing the nonvolatile semiconductor device and manipulating the nonvolatile semiconductor device are provided.
    Type: Application
    Filed: February 4, 2016
    Publication date: June 2, 2016
    Inventors: Ya Jui Lee, Kuan Fu Chen
  • Patent number: 9286984
    Abstract: A nonvolatile semiconductor device is provided that includes a substrate and a plurality of blocks forming a string. Each block is positioned on the substrate and includes a plurality of word lines disposed on the substrate. The string includes a single ground select line disposed at one side of the plurality of blocks, and a single string select line is disposed at another side of the plurality of blocks. In some embodiments, the word lines of the plurality of blocks define gaps separating each block of the string from neighboring blocks of the string. One or more dummy word lines may be disposed in each gap between blocks of the string. Corresponding methods of manufacturing the nonvolatile semiconductor device and manipulating the nonvolatile semiconductor device are provided.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: March 15, 2016
    Assignee: Macronix International Co., Ltd.
    Inventors: Ya Jui Lee, Kuan Fu Chen
  • Publication number: 20160005468
    Abstract: A nonvolatile semiconductor device is provided that includes a substrate and a plurality of blocks forming a string. Each block is positioned on the substrate and includes a plurality of word lines disposed on the substrate. The string includes a single ground select line disposed at one side of the plurality of blocks, and a single string select line is disposed at another side of the plurality of blocks. In some embodiments, the word lines of the plurality of blocks define gaps separating each block of the string from neighboring blocks of the string. One or more dummy word lines may be disposed in each gap between blocks of the string. Corresponding methods of manufacturing the nonvolatile semiconductor device and manipulating the nonvolatile semiconductor device are provided.
    Type: Application
    Filed: July 7, 2014
    Publication date: January 7, 2016
    Inventors: Ya Jui Lee, Kaun Fu Chen
  • Patent number: 8741754
    Abstract: A fabricating method of a non-volatile memory is provided. A tunneling dielectric layer and a first conductive layer are sequentially formed on a substrate. Isolation structures are formed in the first conductive layer, the tunneling dielectric layer and the substrate. The first conductive layer is patterned to form protruding portions. A portion of the isolation structures is removed, so that a top surface of each isolation structure is disposed between a top surface of the first conductive layer and a surface of the substrate. An inter-gate dielectric layer is formed on the substrate. A second conductive layer is formed on the inter-gate dielectric layer. The second conductive layer is patterned to form control gates, and the first conductive layer is patterned to form floating gates. The protruding portion of each floating gate is fully covered and surrounded by the control gate in any direction.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: June 3, 2014
    Assignee: Powerchip Technology Corporation
    Inventors: Ya-Jui Lee, Ying-Chia Lin
  • Patent number: 8502297
    Abstract: A non-volatile memory having a tunneling dielectric layer, a floating gate, a control gate, an inter-gate dielectric layer and a first doping region and a second doping region is provided. The tunneling dielectric layer is disposed on a substrate. The floating gate is disposed on the tunneling dielectric layer, and has a protruding portion. The control gate is disposed over the floating gate to cover and surround the protruding portion. The protruding portion of the floating gate is fully covered and surrounded by the control gate in any direction, including extending directions of bit lines, word lines and an included angle formed between the word line and the bit line. The inter-gate dielectric layer is disposed between the floating gate and the control gate. The first doping region and the second doping region are respectively disposed in the substrate at two sides of the control gate.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: August 6, 2013
    Assignee: Powerchip Technology Corporation
    Inventors: Ya-Jui Lee, Ying-Chia Lin