Patents by Inventor Ya-Jyuan Hung

Ya-Jyuan Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210074917
    Abstract: A method of forming a resistive random access memory cell includes the following steps. A first electrode layer, a blanket resistive switching material layer and a second electrode layer are formed on a layer sequentially. The second electrode layer is patterned to form a second electrode. The blanket resistive switching material layer is patterned to form a resistive switching material layer. An oxygen implanting process is performed to implant oxygen in two sidewall parts of the resistive switching material layer.
    Type: Application
    Filed: October 1, 2019
    Publication date: March 11, 2021
    Inventors: Shih-Wei Su, Da-Jun Lin, Bin-Siang Tsai, Ya-Jyuan Hung, Ting-An Chien
  • Publication number: 20200395413
    Abstract: A memory cell includes a first conductive line, a lower electrode, a carbon nano-tube (CNT) layer, a middle electrode, a resistive layer, a top electrode and a second conductive line. The first conductive line is disposed over a substrate. The lower electrode is disposed over the first conductive line. The carbon nano-tube (CNT) layer is disposed over the lower electrode. The middle electrode is disposed over the carbon nano-tube layer, thereby the lower electrode, the carbon nano-tube (CNT) layer and the middle electrode constituting a nanotube memory part . The resistive layer is disposed over the middle electrode. The top electrode is disposed over the resistive layer, thereby the middle electrode, the resistive layer and the top electrode constituting a resistive memory part. The second conductive line is disposed over the top electrode.
    Type: Application
    Filed: July 17, 2019
    Publication date: December 17, 2020
    Inventors: Da-Jun Lin, Bin-Siang Tsai, Ya-Jyuan Hung, Chin-Chia Yang, Ting-An Chien
  • Publication number: 20190229053
    Abstract: A manufacturing method of a metal-insulator-metal (MIM) capacitor structure includes the following steps. A bottom plate is formed. A first conductive layer is patterned to be the bottom plate, and the first conductive layer includes a metal element. An interface layer is formed on the first conductive layer by performing a nitrous oxide (N2O) treatment on a top surface of the first conductive layer. The interface layer includes oxygen and the metal element of the first conductive layer. A dielectric layer is formed on the interface layer. A top plate is formed on the dielectric layer. The metal-insulator-metal capacitor structure includes the bottom plate, the interface layer disposed on the bottom plate, the dielectric layer disposed on the interface layer, and the top plate disposed on the dielectric layer.
    Type: Application
    Filed: January 22, 2018
    Publication date: July 25, 2019
    Inventors: Ya-Jyuan Hung, Ai-Sen Liu, Bin-Siang Tsai, Chin-Fu Lin, Chun-Yuan Wu
  • Patent number: 10008409
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a dielectric layer on a substrate; forming a stop layer between the dielectric layer and the substrate, wherein the stop layer contacts the substrate directly and the dielectric layer covers the top surface of the stop layer; forming an opening in the dielectric layer, wherein the dielectric layer comprises a damaged layer adjacent to the opening; forming a dielectric protective layer in the opening; forming a metal layer in the opening; removing the damaged layer and the dielectric protective layer to form a void, wherein the void exposes a top surface of the substrate; and forming a cap layer on and covering the dielectric layer, the void, and the metal layer.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: June 26, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chich-Neng Chang, Ya-Jyuan Hung, Bin-Siang Tsai
  • Publication number: 20180012793
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a dielectric layer on a substrate; forming a stop layer between the dielectric layer and the substrate, wherein the stop layer contacts the substrate directly and the dielectric layer covers the top surface of the stop layer; forming an opening in the dielectric layer, wherein the dielectric layer comprises a damaged layer adjacent to the opening; forming a dielectric protective layer in the opening; forming a metal layer in the opening; removing the damaged layer and the dielectric protective layer to form a void, wherein the void exposes a top surface of the substrate; and forming a cap layer on and covering the dielectric layer, the void, and the metal layer.
    Type: Application
    Filed: September 25, 2017
    Publication date: January 11, 2018
    Inventors: Chich-Neng Chang, Ya-Jyuan Hung, Bin-Siang Tsai
  • Patent number: 9812352
    Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a dielectric layer is formed on the substrate, and an opening is formed in the dielectric layer, in which the dielectric layer includes a damaged layer adjacent to the opening. Next, a dielectric protective layer is formed in the opening, a metal layer is formed in the opening, and the damaged layer and the dielectric protective layer are removed.
    Type: Grant
    Filed: January 31, 2016
    Date of Patent: November 7, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chich-Neng Chang, Ya-Jyuan Hung, Bin-Siang Tsai
  • Publication number: 20170200632
    Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a dielectric layer is formed on the substrate, and an opening is formed in the dielectric layer, in which the dielectric layer includes a damaged layer adjacent to the opening. Next, a dielectric protective layer is formed in the opening, a metal layer is formed in the opening, and the damaged layer and the dielectric protective layer are removed.
    Type: Application
    Filed: January 31, 2016
    Publication date: July 13, 2017
    Inventors: Chich-Neng Chang, Ya-Jyuan Hung, Bin-Siang Tsai
  • Patent number: 8486790
    Abstract: A manufacturing method for a metal gate includes providing a substrate having a dielectric layer and a polysilicon layer formed thereon, the polysilicon layer, forming a protecting layer on the polysilicon layer, forming a patterned hard mask on the protecting layer, performing a first etching process to etch the protecting layer and the polysilicon layer to form a dummy gate having a first height on the substrate, forming a multilayered dielectric structure covering the patterned hard mask and the dummy gate, removing the dummy gate to form a gate trench on the substrate, and forming a metal gate having a second height in the gate trench. The second height of the metal gate is substantially equal to the first height of the dummy gate.
    Type: Grant
    Filed: July 18, 2011
    Date of Patent: July 16, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Po-Cheng Huang, Kuo-Chih Lai, Ching-I Li, Yu-Shu Lin, Ya-Jyuan Hung, Yen-Liang Lu, Yu-Wen Wang, Hsin-Chih Yu
  • Patent number: 8431473
    Abstract: A method for fabricating a semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a dielectric layer on the substrate, wherein the dielectric layer comprises metal interconnects therein; forming a top metal layer on the dielectric layer; and forming a passivation layer on the top metal layer through high-density plasma chemical vapor deposition (HDPCVD) process.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: April 30, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Shu-Hui Hu, Shih-Feng Su, Hui-Shen Shih, Chih-Chien Liu, Po-Chun Chen, Ya-Jyuan Hung, Bin-Siang Tsai, Chin-Fu Lin
  • Publication number: 20130023098
    Abstract: A manufacturing method for a metal gate includes providing a substrate having a dielectric layer and a polysilicon layer formed thereon, the polysilicon layer, forming a protecting layer on the polysilicon layer, forming a patterned hard mask on the protecting layer, performing a first etching process to etch the protecting layer and the polysilicon layer to form a dummy gate having a first height on the substrate, forming a multilayered dielectric structure covering the patterned hard mask and the dummy gate, removing the dummy gate to form a gate trench on the substrate, and forming a metal gate having a second height in the gate trench. The second height of the metal gate is substantially equal to the first height of the dummy gate.
    Type: Application
    Filed: July 18, 2011
    Publication date: January 24, 2013
    Inventors: Po-Cheng Huang, Kuo-Chih Lai, Ching-I Li, Yu-Shu Lin, Ya-Jyuan Hung, Yen-Liang Lu, Yu-Wen Wang, Hsin-Chih Yu
  • Publication number: 20130009288
    Abstract: A method for fabricating a semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a dielectric layer on the substrate, wherein the dielectric layer comprises metal interconnects therein; forming a top metal layer on the dielectric layer; and forming a passivation layer on the top metal layer through high-density plasma chemical vapor deposition (HDPCVD) process.
    Type: Application
    Filed: July 7, 2011
    Publication date: January 10, 2013
    Inventors: Shu-Hui Hu, Shih-Feng Su, Hui-Shen Shih, Chih-Chien Liu, Po-Chun Chen, Ya-Jyuan Hung, Bin-Siang Tsai, Chin-Fu Lin