Abstract: An apparatus for noise reduction in audio signal processing includes a power amplifier, a zero-crossing detector, and a threshold detector. The power amplifier has an input signal terminal for receiving an audio input signal and an output signal terminal. The audio input signal is a digital-to-analog converted version according to a version of a digital audio signal. The power amplifier has an analog gain which is controllable in response to an analog gain control signal. The zero-crossing detector determines a zero-crossing detection signal according to an internal signal provided between the input signal terminal and the output signal terminal. The threshold detector determines a gain setting according to the digital audio signal and the zero-crossing detection signal to generate the analog gain control signal indicating the gain setting, wherein the threshold detector controls the analog gain of the power amplifier according to the analog gain control signal.

Abstract: An apparatus for noise reduction in audio signal processing includes a power amplifier, a zero-crossing detector, and a threshold detector. The power amplifier has an input signal terminal for receiving an audio input signal and an output signal terminal. The audio input signal is a digital-to-analog converted version according to a version of a digital audio signal. The power amplifier has an analog gain which is controllable in response to an analog gain control signal. The zero-crossing detector determines a zero-crossing detection signal according to an internal signal provided between the input signal terminal and the output signal terminal. The threshold detector determines a gain setting according to the digital audio signal and the zero-crossing detection signal to generate the analog gain control signal indicating the gain setting, wherein the threshold detector controls the analog gain of the power amplifier according to the analog gain control signal.

Abstract: A voltage converter comprising: a bootstrap circuit, comprising an output capacitor, an error amplifier, a charging control circuit and a charging circuit. The charging control circuit comprises: a detection circuit, configured to detect an output voltage of the output capacitor to generate a detection signal; and a power limiting circuit, configured to clamp an output voltage of the error amplifier to a specific range based on the detection signal. The charging circuit is configured to generate a charging signal according the output voltage of the error amplifier to the bootstrap circuit, to charge the output capacitor.

Abstract: A voltage converter comprising: a bootstrap circuit, comprising an output capacitor, an error amplifier, a charging control circuit and a charging circuit. The charging control circuit comprises: a detection circuit, configured to detect an output voltage of the output capacitor to generate a detection signal; and a power limiting circuit, configured to clamp an output voltage of the error amplifier to a specific range based on the detection signal . The charging circuit is configured to generate a charging signal according the output voltage of the error amplifier to the bootstrap circuit, to charge the output capacitor.

Abstract: An over charge protection method applied to a voltage converter which can operate in a quaternary modulation mode (Q mode) or a ternary modulation mode (T mode). The over charge protection method comprises: (a) determining whether the voltage converter operates in the Q mode or the T mode; and (b) setting a current threshold of the voltage converter to a first over current threshold if the voltage converter operates in the T mode; and (c) setting the current threshold to a second over current threshold if the voltage converter operates in the Q mode, wherein the first current threshold is smaller than the second over current threshold.

Abstract: A pulse width modulation output stage incorporates a half bridge output stage, a gate control circuit, a detection circuit, and a control logic. The half bridge output stage has a first transistor and a second transistor connected in series between a power supply node and a ground node. The gate control circuit outputs a pulse width modulation signal to drive the first transistor and the second transistor. The detection circuit detects whether or not a glitch occurs in one of the gate voltages of the first and second transistor so as to generate a control code. The logic circuit varies the delay time of the pulse width modulation signal based on the control code.

Abstract: A pulse width modulation output stage incorporates a half bridge output stage, a gate control circuit, a detection circuit, and a control logic. The half bridge output stage has a first transistor and a second transistor connected in series between a power supply node and a ground node. The gate control circuit outputs a pulse width modulation signal to drive the first transistor and the second transistor. The detection circuit detects whether or not a glitch occurs in one of the gate voltages of the first and second transistor so as to generate a control code. The logic circuit varies the delay time of the pulse width modulation signal based on the control code.