Abstract: Embodiments of strain-balanced superlattice infrared detector devices and their fabrication are disclosed. In one embodiment, an infrared detector device includes a first contact layer, and absorber superlattice region, a wider gap unipolar barrier region, and a second contact layer. The absorber superlattice region has a period defined by a first InAs layer, strain-balancing structure, a second InAs layer, and an InAsSb layer. The strain-balancing structure comprises an arbitrary alloy layer sequence containing at least one constituent element of aluminum or phosphor, e.g., InGaAs, AlInAs InAsP. In another embodiment, the absorber superlattice region has a period defined by a first InAs layer, first strain-balancing structure, a second InAs layer, a first GaSb layer, a second strain-balancing structure, and a second GaSb layer. The first strain-balancing structure includes at least one constituent element of aluminum or phosphor, e.g., InGaAs, AlInAs InAsP.

Abstract: Each LED in an array of LEDs mounted on a submount wafer has at least a first semiconductor layer exposed and connected to a first electrode of each LED. The submount wafer has a first metal portion bonded to the first electrode of each LED for providing an energization current to each LED. The submount wafer also has a second metal portion running along and proximate to the first metal portion but not electrically connected to the first metal portion. The second metal portion may be interdigitated with the first metal portion. The second metal portion is connected to a bias voltage. When the wafer is immersed in an electrically conductive solution for electrochemical (EC) etching of the exposed first semiconductor layer, the solution electrically connects the second metal portion to the first metal portion for biasing the first semiconductor layer during the EC etching.

Abstract: Diode barrier infrared detector devices and superlattice barrier structures are disclosed. In one embodiment, a diode barrier infrared detector device includes a first contact layer, an absorber layer adjacent to the first contact layer, and a barrier layer adjacent to the absorber layer, and a second contact layer adjacent to the barrier layer. The barrier layer includes a diode structure formed by a p-n junction formed within the barrier layer. The barrier layer may be such that there is substantially no barrier to minority carrier holes. In another embodiment, a diode barrier infrared detector device includes a first contact layer, an absorber layer adjacent to the first contact layer, a barrier layer adjacent to the absorber layer, and a diode structure adjacent to the barrier layer. The diode structure includes a second contact layer.

Abstract: A light emitting diode (LED) structure (10) has semiconductor layers, including a p-type layer, an active layer, and an n-type layer. The p-type layer has a bottom surface, and the n-type layer has a top surface through which light is emitted. Portions of the p-type layer and active layer are etched away to expose the n-type layer. The surface of the LED is patterned with a photoresist, and copper is plated over the exposed surfaces to form p and n electrodes electrically contacting their respective semi-conductor layers. There is a gap between the n and p electrodes. To provide mechanical support of the semiconductor layers between the gap, a dielectric layer (34) is formed in the gap followed by filling the gap with a metal (42). The metal is patterned to form stud bumps (40, 42, 44) that substantially cover the bottom surface of the LED die, but do not short the electrodes. The substantially uniform coverage supports the semiconductor layer during subsequent process steps.

Abstract: A light emitting diode (LED) structure has semiconductor layers, including a p-type layer, an active layer, and an n-Type layer. The p-type layer has a bottom surface, and the n-type layer has a top surface though which light is emitted. A copper layer has a first portion electrically connected to and opposing the bottom surface of the p-type layer. A dielectric wall extends through the copper layer to isolate a second portion of the copper layer from the first portion. A metal shunt electrically connects the second portion of the copper layer to the top surface of the n-type layer. P-metal electrodes electrically connect to the first portion, and n-metal electrodes electrically connect to the second portion, wherein the LED structure forms a flip chip. Other embodiments of the methods and structures are also described.

Abstract: Elements are added to a light emitting device to reduce the stress within the light emitting device caused by thermal cycling. Alternatively, or additionally, materials are selected for forming contacts within a light emitting device based on their coefficient of thermal expansion and their relative cost, copper alloys being less expensive than gold, and providing a lower coefficient of thermal expansion than copper. Elements of the light emitting device may also be structured to distribute the stress during thermal cycling.

Abstract: Each LED in an array of LEDs mounted on a submount wafer has at least a first semiconductor layer exposed and connected to a first electrode of each LED. The submount wafer has a first metal portion bonded to the first electrode of each LED for providing an energization current to each LED. The submount wafer also has a second metal portion running along and proximate to the first metal portion but not electrically connected to the first metal portion. The second metal portion may be interdigitated with the first metal portion. The second metal portion is connected to a bias voltage. When the wafer is immersed in an electrically conductive solution for electrochemical (EC) etching of the exposed first semiconductor layer, the solution electrically connects the second metal portion to the first metal portion for biasing the first semiconductor layer during the EC etching.

Abstract: A transient voltage suppressor circuit is disclosed for a plurality (N) of LEDs connected in series. Only one zener diode is created for connection to each node between LEDs, and a pair of zener diodes (the “end” zener diodes) are connected to the two pins (anode and cathode pads) of the series string. Therefore, only N+1 zener diodes are used. The end zener diodes (Q1 and Qn+1) effectively create back-to-back zener diodes across the two pins since the zener diodes share a common p+ substrate. The n+ regions of the end zener diodes Q1 and Qn+1 have the highest breakdown voltage requirement and must be placed relatively far apart. Adjacent n+ regions of the intermediate zener diodes have a much lower breakdown voltage requirement so may be located close together. The zener diodes may be placed within a very small footprint or can be larger for better suppressor performance.

Abstract: An array of housings with housing bodies and lenses is molded, or an array of housing bodies is molded and bonded with lenses to form an array of housings with housing bodies and lenses. Light-emitting diodes (LEDs) are attached to the housings in the array. An array of metal pads may be bonded to the back of the array or insert molded with the housing array to form bond pads on the back of the housings. The array is singulated to form individual LED modules.

Abstract: A transient voltage suppressor circuit is disclosed for a plurality (N) of LEDs connected in series. Only one zener diode is created for connection to each node between LEDs, and a pair of zener diodes (the “end” zener diodes) are connected to the two pins (anode and cathode pads) of the series string. Therefore, only N+1 zener diodes are used. The end zener diodes (Q1 and Qn+1) effectively create back-to-back zener diodes across the two pins since the zener diodes share a common p+ substrate. The n+ regions of the end zener diodes Q1 and Qn+1 have the highest breakdown voltage requirement and must be placed relatively far apart. Adjacent n+ regions of the intermediate zener diodes have a much lower breakdown voltage requirement so may be located close together. Since there are fewer zener diodes and their spacings may be small, the zener diodes may be placed within a very small footprint or can be larger for better suppressor performance.