Abstract: Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.

Abstract: Integrated circuits may include memory interface circuitry operable to communicate with system memory. The memory interface circuitry may receive data and data strobe signals from system memory during read operations. The memory interface circuitry may include de-skew circuitry and dynamic variation compensation circuitry. The de-skew circuitry may be configured during calibration procedures to reduce skew between the data and data strobe signals. The dynamic variation compensation circuitry may be used in real time to compensate for variations in operating conditions.

Abstract: The optical coupler module for converting and transmitting electrical/optical signals includes a semiconductor substrate, a first film, a second film, an electrical transmission unit, at least one signal conversion unit and an optical waveguide structure. The first film and the second film are formed on opposite surfaces of the semiconductor substrate. The signal conversion unit and the optical waveguide structure are disposed on opposite sides of the semiconductor substrate. The optical waveguide structure has a reflector and a waveguide body. The optical signal generated from the signal conversion unit sequentially passes the first film, the semiconductor substrate and the second film and enters the optical waveguide structure. Then, the optical signal is reflected by the reflector and transmitted in the waveguide body to be outputted. Alternatively, the optical signal is transmitted in a reverse direction from the optical waveguide structure to the signal conversion unit.

Abstract: A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.

Abstract: A circuit includes a locked loop and a phase offset circuit. The locked loop generates first control signals for controlling a first delay in the locked loop. The phase offset circuit delays an input signal by a second delay that is controlled by second control signals to generate a delayed signal. The phase offset circuit generates the second control signals by adjusting the first control signals to increase the accuracy of the delayed signal with respect to a target phase. The second control signals compensate for at least a portion of a change in the second delay that is caused by a variation in at least one of a process, a supply voltage, and a temperature of the circuit.

Abstract: Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.

Abstract: Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device.

Abstract: A feedback loop circuit includes a phase detector and delay circuits. The phase detector generates an output signal based on a delayed periodic signal. The delay circuits are coupled in a delay chain that delays the delayed periodic signal. Each of the delay circuits includes variable delay blocks and fixed delay blocks that are coupled to form at least two delay paths for an input signal through the delay circuit to generate a delayed output signal. Delays of the variable delay blocks in the delay circuits vary based on the output signal of the phase detector. Each of the delay circuits reroutes the input signal through a different one of the delay paths to generate the delayed output signal based on the output signal of the phase detector during operation of the feedback loop circuit.

Abstract: An optical coupler module includes a semiconductor substrate disposed on the print circuit board; a reflecting trench structure formed on the semiconductor substrate; a reflector formed on a slant surface of the reflecting trench structure; a strip trench structure formed on the semiconductor substrate and connecting with the reflecting trench structure; a thin film disposed on the above-mentioned structure. The optical coupler module further includes a signal conversion unit disposed on the semiconductor substrate and the position of the signal conversion unit corresponds to the reflector; and an optical waveguide structure formed in the trench structures. The optical signal from the signal conversion unit is reflected by the reflector and then transmitted in the optical waveguide structure, or in a reverse direction to reach the signal conversion unit.

Abstract: A feedback loop circuit includes a phase detector and delay circuits. The phase detector generates an output signal based on a delayed periodic signal. The delay circuits are coupled in a delay chain that delays the delayed periodic signal. Each of the delay circuits comprises variable delay blocks and fixed delay blocks that are coupled to form at least two delay paths for an input signal through the delay circuit to generate a delayed output signal. Delays of the variable delay blocks in the delay circuits vary based on the output signal of the phase detector. Each of the delay circuits reroutes the input signal through a different one of the delay paths to generate the delayed output signal based on the output signal of the phase detector during operation of the feedback loop circuit. Each of the variable delay blocks and the fixed delay blocks is inverting.

Abstract: Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device.

Abstract: Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.

Abstract: An optical transmission module includes a semiconductor substrate, a first film layer, an electronic component layer and a waveguide structure. The electronic component layer is used for converting a first electrical signal into an optical signal. The waveguide structure is formed on the first film layer, and includes a first reflective surface, a waveguide body and a second reflective surface. After the optical signal is transmitted through the semiconductor substrate and the first film layer and enters the waveguide structure, the optical signal is reflected by the first reflective surface, transmitted within the waveguide body and reflected by the second reflective surface. After the optical signal reflected by the second reflective surface is transmitted through the first film layer and the semiconductor substrate and received by the electronic component layer, the optical signal is converted into a second electrical signal by the electronic component layer.

Abstract: The optical coupler module for converting and transmitting electrical/optical signals includes a semiconductor substrate, a first film, a second film, an electrical transmission unit, at least one signal conversion unit and an optical waveguide structure. The first film and the second film are formed on opposite surfaces of the semiconductor substrate. The signal conversion unit and the optical waveguide structure are disposed on opposite sides of the semiconductor substrate. The optical waveguide structure has a reflector and a waveguide body. The optical signal generated from the signal conversion unit sequentially passes the first film, the semiconductor substrate and the second film and enters the optical waveguide structure. Then, the optical signal is reflected by the reflector and transmitted in the waveguide body to be outputted. Alternatively, the optical signal is transmitted in a reverse direction from the optical waveguide structure to the signal conversion unit.

Abstract: Delay associated with each of two signals along respective transmission paths is accurately measured using a delay measurement circuit that is fabricated in situ on the actual device where the circuitry for propagating the two signals is fabricated. Thus, the measured delay associated with each of the two signals is subject to the same fabrication-dependent attributes that affect the actual circuitry through which the two signals will be propagated during operation of the device. The skew between the two signals is quantified as the difference in the measured delays. Coarse and fine delay modules are defined within the transmission path of each of the two signals. Based on the measured skew between the two signals, the coarse and fine delay modules are appropriately set to compensate for the skew. The appropriately settings for the coarse and fine delay modules can be stored in non-volatile memory elements.

Abstract: Circuits, methods, and apparatus that isolate an input register from spurious transitions on a DQS signal. One example receives an enable signal from a core. A logic circuit, which may be referred to as a one-half period circuit, shortens enable pulses at their front end by one-half a period. The shortened enable signal is passed to a storage element such as a register. Active pulses of the shortened enable signal clear the register, which provides a control signal closing a switch, such as an AND gate. The switch passes the DQS signal to the input register when closed and isolates the input register from the DQS signal when open. The shortened enable signal prevents the switch from opening early and passing spurious transitions on the DQS signal, for example during back-to-back non-consecutive read cycles.

Abstract: Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming element between input and core circuits. The retiming element is calibrated by incrementally sweeping a delay and receiving data at each increment. Minimum and maximum delays where data is received without errors are averaged. This average can then be used to adjust the timing of a circuit element inserted in an input path between an input register clocked by an input strobe signal and an output register clocked by a core clock signal. In one example, an input signal may be delayed by an amount corresponding to the delay setting. In other examples, each input signal is registered using an intermediate register between the input register and the output register, where a clock signal is delayed by an amount corresponding to the delay setting.

Abstract: Circuits and a method for correcting duty cycle distortions in an integrated circuit (IC) are disclosed. The IC includes a splitter circuit that is coupled to receive a clock signal. The clock signal is split into two different clock signals. One of the clock signals is an inverted version of the other. A delay circuit is coupled to each of the clock signals. Each of the delay circuits generates a delayed version of the corresponding clock signal. A corrector circuit is coupled to receive both the delayed versions of the clock signals. The corrector circuit generates a clock output signal with a corrected duty cycle.

Abstract: Circuits, methods, and apparatus that provide the calibration of input and output circuits for a high-speed memory interface. Timing errors caused by the fly-by routing of a clock signal provided by the memory interface are calibrated for both read and write paths. This includes adjusting read and write DQS signal timing for each DQ/DQS group, as well as inserting or bypassing registers when timing errors are more than one clock cycle. Timing skew caused by trace and driver mismatches between CK, DQ, and DQS signals are compensated for. One or more of these calibrations may be updated by a tracking routine during device operation.

Abstract: A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.