Patents by Inventor Yang Kern Jonathan Tan

Yang Kern Jonathan Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device and method of forming wire studs as vertical interconnect in FO-WLP
    Patent number: 10446523
    Abstract: A semiconductor device has a substrate and semiconductor die disposed over a first surface of the substrate. A wire stud is attached to the first surface of the substrate. The wire stud includes a base portion and stem portion. A bonding pad is formed over a second surface of the substrate. An encapsulant is deposited over the substrate, semiconductor die, and wire stud. A portion of the encapsulant is removed by LDA to expose the wire stud. A portion of the encapsulant is removed by LDA to expose the substrate. An interconnect structure is formed over the encapsulant and electrically connected to the wire stud and semiconductor die. A bump is formed over the interconnect structure. A semiconductor package is disposed over the encapsulant and electrically connected to the substrate. A discrete semiconductor device is disposed over the encapsulant and electrically connected to the substrate.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: October 15, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Pandi C. Marimuthu, Sheila Marie L. Alvarez, Yaojian Lin, Jose A. Caparas, Yang Kern Jonathan Tan
  • Semiconductor Device and Method of Forming Wire Studs as Vertical Interconnect in FO-WLP
    Publication number: 20160336299
    Abstract: A semiconductor device has a substrate and semiconductor die disposed over a first surface of the substrate. A wire stud is attached to the first surface of the substrate. The wire stud includes a base portion and stem portion. A bonding pad is formed over a second surface of the substrate. An encapsulant is deposited over the substrate, semiconductor die, and wire stud. A portion of the encapsulant is removed by LDA to expose the wire stud. A portion of the encapsulant is removed by LDA to expose the substrate. An interconnect structure is formed over the encapsulant and electrically connected to the wire stud and semiconductor die. A bump is formed over the interconnect structure. A semiconductor package is disposed over the encapsulant and electrically connected to the substrate. A discrete semiconductor device is disposed over the encapsulant and electrically connected to the substrate.
    Type: Application
    Filed: July 25, 2016
    Publication date: November 17, 2016
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Pandi C. Marimuthu, Sheila Marie L. Alvarez, Yaojian Lin, Jose A. Caparas, Yang Kern Jonathan Tan
  • Semiconductor device having wire studs as vertical interconnect in FO-WLP
    Patent number: 9443797
    Abstract: A semiconductor device has a substrate and semiconductor die disposed over a first surface of the substrate. A wire stud is attached to the first surface of the substrate. The wire stud includes a base portion and stem portion. A bonding pad is formed over a second surface of the substrate. An encapsulant is deposited over the substrate, semiconductor die, and wire stud. A portion of the encapsulant is removed by LDA to expose the wire stud. A portion of the encapsulant is removed by LDA to expose the substrate. An interconnect structure is formed over the encapsulant and electrically connected to the wire stud and semiconductor die. A bump is formed over the interconnect structure. A semiconductor package is disposed over the encapsulant and electrically connected to the substrate. A discrete semiconductor device is disposed over the encapsulant and electrically connected to the substrate.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 13, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Pandi C. Marimuthu, Sheila Marie L. Alvarez, Yaojian Lin, Jose A. Caparas, Yang Kern Jonathan Tan
  • Semiconductor Device and Method of Forming Wire Studs as Vertical Interconnect in FO-WLP
    Publication number: 20140077364
    Abstract: A semiconductor device has a substrate and semiconductor die disposed over a first surface of the substrate. A wire stud is attached to the first surface of the substrate. The wire stud includes a base portion and stem portion. A bonding pad is formed over a second surface of the substrate. An encapsulant is deposited over the substrate, semiconductor die, and wire stud. A portion of the encapsulant is removed by LDA to expose the wire stud. A portion of the encapsulant is removed by LDA to expose the substrate. An interconnect structure is formed over the encapsulant and electrically connected to the wire stud and semiconductor die. A bump is formed over the interconnect structure. A semiconductor package is disposed over the encapsulant and electrically connected to the substrate. A discrete semiconductor device is disposed over the encapsulant and electrically connected to the substrate.
    Type: Application
    Filed: March 15, 2013
    Publication date: March 20, 2014
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Pandi C. Marimuthu, Sheila Marie L. Alvarez, Yaojian Lin, Jose A. Caparas, Yang Kern Jonathan Tan