Patents by Inventor Yangyin Chen

Yangyin Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11094653
    Abstract: A bonded assembly and a method of forming a bonded assembly includes providing a first semiconductor die including a first substrate, first semiconductor devices, and first bonding pads that are electrically connected to a respective node of the first semiconductor devices, providing a second semiconductor die including a second substrate, second semiconductor devices, and second bonding pads that are electrically connected to a respective node of the second semiconductor devices, forming a dielectric bonding pattern definition layer including bonding pattern definition openings therethrough over the second bonding pads, and bonding the second bonding pads to the first bonding pads, where the first metal pads expand through the bonding pattern definition openings and are bonded to a respective one of the second bonding pads.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: August 17, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Chen Wu, Peter Rabkin, Yangyin Chen, Masaaki Higashitani
  • Patent number: 11037908
    Abstract: A bonded assembly includes a first semiconductor die including a first substrate, first semiconductor devices located on the first substrate, first dielectric material layers located on the first semiconductor devices and embedding first metal interconnect structures, and first through-substrate via structures extending through the first substrate and contacting a respective first metal interconnect structure. Each of the first through-substrate via structures laterally surrounds a respective core cavity that contains a void or a dielectric fill material portion.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: June 15, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Chen Wu, Peter Rabkin, Yangyin Chen, Masaaki Higashitani
  • Publication number: 20210159215
    Abstract: A bonded assembly includes a first die containing first bonding pads having sidewalls that are laterally bonded to sidewalls of second bonding pads of a second die.
    Type: Application
    Filed: November 25, 2019
    Publication date: May 27, 2021
    Inventors: Chen WU, Peter RABKIN, Yangyin CHEN, Masaaki HIGASHITANI
  • Publication number: 20210143115
    Abstract: A bonded assembly and a method of forming a bonded assembly includes providing a first semiconductor die including a first substrate, first semiconductor devices, and first bonding pads that are electrically connected to a respective node of the first semiconductor devices, providing a second semiconductor die including a second substrate, second semiconductor devices, and second bonding pads that are electrically connected to a respective node of the second semiconductor devices, forming a dielectric bonding pattern definition layer including bonding pattern definition openings therethrough over the second bonding pads, and bonding the second bonding pads to the first bonding pads, where the first metal pads expand through the bonding pattern definition openings and are bonded to a respective one of the second bonding pads.
    Type: Application
    Filed: November 13, 2019
    Publication date: May 13, 2021
    Inventors: Chen WU, Peter RABKIN, Yangyin CHEN, Masaaki HIGASHITANI
  • Publication number: 20210066317
    Abstract: A semiconductor structure includes a first semiconductor die containing a recesses, and a second semiconductor die which is embedded in the recess in the first semiconductor die and is bonded to the first semiconductor die.
    Type: Application
    Filed: August 27, 2019
    Publication date: March 4, 2021
    Inventors: Chen WU, Peter RABKIN, Yangyin CHEN, Masaaki HIGASHITANI
  • Publication number: 20210028148
    Abstract: A bonded assembly includes a first semiconductor die including a first substrate, first semiconductor devices located on the first substrate, first dielectric material layers located on the first semiconductor devices and embedding first metal interconnect structures, and first through-substrate via structures extending through the first substrate and contacting a respective first metal interconnect structure. Each of the first through-substrate via structures laterally surrounds a respective core cavity that contains a void or a dielectric fill material portion.
    Type: Application
    Filed: July 25, 2019
    Publication date: January 28, 2021
    Inventors: Chen WU, Peter RABKIN, Yangyin CHEN, Masaaki HIGASHITANI
  • Patent number: 10756186
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. The sacrificial material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings are formed through the alternating stack. A memory film is formed within each memory openings. A silicon-germanium alloy layer including germanium at an atomic concentration less than 25% is deposited within each memory opening. An oxidation process is performed on the silicon-germanium alloy layer. A vertical semiconductor channel including an unoxidized remaining material portion of the silicon-germanium alloy layer is formed, which includes germanium at an atomic concentration greater than 50%.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: August 25, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yangyin Chen, Christopher Petti
  • Patent number: 10734408
    Abstract: A non-volatile memory system is provided that includes a plurality of NAND strings of non-volatile storage elements, each non-volatile storage element including a control gate, a tunneling layer, a floating gate, and a blocking layer including a ferroelectric material. The tunneling layer is disposed between the control gate and the floating gate, and the floating gate is disposed between the tunneling layer and the blocking layer.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: August 4, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Yingda Dong, Yangyin Chen, Yukihiro Sakotsubo
  • Patent number: 10559588
    Abstract: A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips laterally spaced apart among one another by line trenches and a two-dimensional array of memory stack structures and a two-dimensional array of dielectric pillar structures located in the line trenches. Each line trench is filled with laterally alternating sequence of memory stack structures and dielectric pillar structures. Each memory stack structure contains a vertical semiconductor channel, a pair of blocking dielectrics contacting outer sidewalls of the vertical semiconductor channel, a pair of charge storage layers contacting outer sidewalls of the pair of blocking dielectrics, and a pair of tunneling dielectrics contacting outer sidewalls of the pair of charge storage layers.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: February 11, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yingda Dong, Yangyin Chen, James Kai
  • Publication number: 20200020704
    Abstract: A non-volatile memory system is provided that includes a plurality of NAND strings of non-volatile storage elements, each non-volatile storage element including a control gate, a tunneling layer, a floating gate, and a blocking layer including a ferroelectric material. The tunneling layer is disposed between the control gate and the floating gate, and the floating gate is disposed between the tunneling layer and the blocking layer.
    Type: Application
    Filed: September 24, 2019
    Publication date: January 16, 2020
    Applicant: SanDisk Technologies LLC
    Inventors: Yingda Dong, Yangyin Chen, Yukihiro Sakotsubo
  • Patent number: 10461095
    Abstract: A non-volatile storage element is provided that includes a control gate, a blocking layer including a ferroelectric material, a charge storage region, and a tunneling layer. The blocking layer is disposed between the control gate and the charge storage region, and the charge storage region is disposed between the tunneling layer and the blocking layer.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: October 29, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Yingda Dong, Yangyin Chen, Yukihiro Sakotsubo
  • Patent number: 10453862
    Abstract: A memory cell is provided that includes a control gate, a tunneling layer, a charge storage region, a blocking layer including a ferroelectric material, a semiconductor channel, and a source region and a drain region each disposed adjacent the semiconductor channel. The tunneling layer is disposed between the control gate and the charge storage region, the charge storage region is disposed between the tunneling layer and the blocking layer, and the blocking layer is disposed above the semiconductor channel.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: October 22, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Yingda Dong, Yangyin Chen, Yukihiro Sakotsubo
  • Patent number: 10453861
    Abstract: A non-volatile storage element including a control gate, a tunneling layer, a charge storage region, and a blocking layer including a ferroelectric material. The tunneling layer is disposed between the control gate and the charge storage region, and the charge storage region is disposed between the tunneling layer and the blocking layer.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: October 22, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Yingda Dong, Yangyin Chen, Yukihiro Sakotsubo
  • Publication number: 20190319100
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. The sacrificial material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings are formed through the alternating stack. A memory film is formed within each memory openings. A silicon-germanium alloy layer including germanium at an atomic concentration less than 25% is deposited within each memory opening. An oxidation process is performed on the silicon-germanium alloy layer. A vertical semiconductor channel including an unoxidized remaining material portion of the silicon-germanium alloy layer is formed, which includes germanium at an atomic concentration greater than 50%.
    Type: Application
    Filed: April 12, 2018
    Publication date: October 17, 2019
    Inventors: Yangyin Chen, Christopher Petti
  • Publication number: 20190304988
    Abstract: A non-volatile storage element is provided that includes a control gate, a blocking layer including a ferroelectric material, a charge storage region, and a tunneling layer. The blocking layer is disposed between the control gate and the charge storage region, and the charge storage region is disposed between the tunneling layer and the blocking layer.
    Type: Application
    Filed: March 28, 2018
    Publication date: October 3, 2019
    Applicant: SanDisk Technologies LLC
    Inventors: Yingda Dong, Yangyin Chen, Yukihiro Sakotsubo
  • Publication number: 20190304987
    Abstract: A memory cell is provided that includes a control gate, a tunneling layer, a charge storage region, a blocking layer including a ferroelectric material, a semiconductor channel, and a source region and a drain region each disposed adjacent the semiconductor channel.
    Type: Application
    Filed: March 28, 2018
    Publication date: October 3, 2019
    Inventors: Yingda Dong, Yangyin Chen, Yukihiro Sakotsubo
  • Publication number: 20190304986
    Abstract: A non-volatile storage element including a control gate, a tunneling layer, a charge storage region, and a blocking layer including a ferroelectric material. The tunneling layer is disposed between the control gate and the charge storage region, and the charge storage region is disposed between the tunneling layer and the blocking layer.
    Type: Application
    Filed: March 28, 2018
    Publication date: October 3, 2019
    Applicant: SanDisk Technologies LLC
    Inventors: Yingda Dong, Yangyin Chen, Yukihiro Sakotsubo
  • Publication number: 20190221575
    Abstract: A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips laterally spaced apart among one another by line trenches and a two-dimensional array of memory stack structures and a two-dimensional array of dielectric pillar structures located in the line trenches. Each line trench is filled with laterally alternating sequence of memory stack structures and dielectric pillar structures. Each memory stack structure contains a vertical semiconductor channel, a pair of blocking dielectrics contacting outer sidewalls of the vertical semiconductor channel, a pair of charge storage layers contacting outer sidewalls of the pair of blocking dielectrics, and a pair of tunneling dielectrics contacting outer sidewalls of the pair of charge storage layers.
    Type: Application
    Filed: May 4, 2018
    Publication date: July 18, 2019
    Inventors: Yingda Dong, Yangyin Chen, James Kai
  • Patent number: 10109679
    Abstract: Systems and methods for fabricating a non-volatile memory with integrated selector devices (or steering devices) are described. Each memory cell within a memory array may be placed in series with a selector device, such as a diode or other non-linear current-voltage device, in order to reduce leakage currents through unselected memory cells during a memory operation. In some cases, fabricating a selector device within a memory hole region may be difficult due to the dimensions of the selector device. A wordline sidewall recess process or a wordline sidewall recess with a replacement metal gate process may be used to integrate selector devices with memory cells outside of the memory hole region. By fabricating non-linear selector devices outside of the memory hole region, the area of the memory array may be reduced.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: October 23, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yangyin Chen, Christopher Petti
  • Patent number: 10038092
    Abstract: A non-volatile memory cell stores 1.5 bits of data in three polarization states. The memory cell may have two ferroelectric layers and three electrodes. The energy bands of the ferroelectric layers are adjusted by providing two of the electrodes with different work functions. The difference in the work functions may be significant, such as at least 0.4-0.6 V or more. Two of the electrodes may have equal or similar work functions. For example, the work functions may be equal within a tolerance of +/?0.1 V. The memory cell can be arranged in various configurations including a FeFET (ferroelectric field effect transistor) and a FeRAM (ferroelectric random access memory). A set of memory cells can be arranged in a string such as a NAND string.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: July 31, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Yangyin Chen, Christopher J Petti