Patents by Inventor Yanjuan Zhan

Yanjuan Zhan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10852956
    Abstract: Embodiments of the invention provide a novel structure of a high-bandwidth-memory command queue of a memory controller with external per-bank refresh and DRAM burst reordering. Where the external per-bank refresh removes some of the unpredictable nature of PBR commands and DRAM burst reordering provides for efficient utilization of memory bandwidth.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: December 1, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ying Li, Xiaofei Li, Yanjuan Zhan, Zhehong Qian, Buying Du
  • Patent number: 10409357
    Abstract: Embodiments of the invention provide a command-oriented method to lower power consumption of PHY during idle time periods. The idle time periods occur because HBM Commands have certain timing windows where there is no data transmission on DFI data signals between the memory controller and the PHY data slice. These windows may be utilized to power down the PHY data slice data path through DFI signal handshaking. In contrast to the conventional low power mode, this method provides an advanced low power mode that can further reduce power consumption in different modes at each suitable idle time based on different command types.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: September 10, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Xiaofei Li, Zhehong Qian, Yanjuan Zhan, Ying Li, Buying Du
  • Patent number: 10297311
    Abstract: Various embodiments provide for determining a delay of a data signal with respect to a data strobe signal within a memory system comprising a memory controller and a memory module. In particular, some embodiments adjust a phase between a data signal and a data strobe signal such that a data eye of the data signal arrives at a receiver latch of a memory module can be centered on a transition of the data strobe signal. By centering the data eye of the data signal with the transition of the data strobe signal, various embodiments can ensure that the data strobe signal transition falls between the leading and trailing edges of the data eye, which in turn permits the memory module to obtain correct data from the memory controller during a write operation.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: May 21, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Wei Yuan, Xiaobo Zhang, Yanjuan Zhan, Yuan Li
  • Patent number: 10203875
    Abstract: A method to initiate Command Address (CA) training on High Memory Bandwidth is provided to optimize CA bus setup and hold times relative to the memory clock. HBM protocol does not define any way to support CA training, but defines a very high working frequency. The high frequency makes it very difficult to ensure the timing on CA Bus-Row/Column command bus and CKE. As such, executing CA training before any normal operation is necessary to ensure the best setup/hold timings. The CA training takes advantage of protocol based instructions to initialize and implement CA training.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: February 12, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Guangxi Ying, Zhehong Qian, Liang Huo, Yanjuan Zhan
  • Patent number: 10162522
    Abstract: Embodiments of the invention provide an approach to implement a single architecture to support high bandwidth memory of pseudo channel mode or legacy channel mode by using a single command channel and single data channel. An address mapping method forces each port transaction to alternatively split to two pseudo channels. Compared to the conventional pseudo channel architecture, the single architecture and pseudo channel rotation eliminates the need for duplicated command traffic logic, and a time division command arbitrator, which greatly reduces both control logic and power consumption of the circuits. Furthermore, pseudo channel rotation improves the utilization of memory bandwidth because the address mapping improves synchronization of the two pseudo channel traffics.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: December 25, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventors: Xiaofei Li, Zhehong Qian, Yanjuan Zhan, Ying Li, Buying Du
  • Patent number: 10067689
    Abstract: According to certain general aspects, the present embodiments relate to methods and apparatuses for performing read and write data path training in HBMs. In accordance with some aspects, embodiments configure HBM mode registers for read and write data path training using an IEEE 1500 interface is simpler than the traditional scenario. In accordance with other aspects, the logic for performing read and write data path training is independent from normal memory access functionality in the host, capable of independently interacting with a PHY core for performing read and write data path training.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: September 4, 2018
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Guangxi Ying, Zhehong Qian, Xiaobo Zhang, Yanjuan Zhan
  • Patent number: 9881664
    Abstract: A method for minimizing skew in a High Bandwidth Memory (HBM) device is provided. The method includes grouping a plurality of information bits of the HBM device into at least two groups of information bits, wherein the plurality of information bits includes a plurality of data bits and a plurality of control bits, and the plurality of information bits are grouped such that each group of the at least two groups includes at least one control bit and the at least two groups form a byte of data. The method further includes delaying the plurality of information bits of each group of the at least two groups during a data transfer operation to minimize the skew between the at least two groups of information bits.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: January 30, 2018
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Guangxi Ying, Yanjuan Zhan, Zhehong Qian, Ying Li