Patents by Inventor Yanli Zhang

Yanli Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9305932
    Abstract: A method of making a monolithic three dimensional NAND string includes providing a first stack of alternating first material layers and second material layers over a major surface of a substrate. The first material layers include first silicon oxide layers, the second material layers include second silicon oxide layers, and the first silicon oxide layers have a different etch rate from the second silicon oxide when exposed to the same etching medium. The first stack includes a back side opening, a front side opening, and at least a portion of a floating gate layer, a tunnel dielectric and a semiconductor channel located in the front side opening. The method also includes selectively removing the first material layers through the back side opening to form back side control gate recesses between adjacent second material layers.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: April 5, 2016
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Senaka Krishna Kanakamedala, Yanli Zhang, Raghuveer S. Makala, Yao-Sheng Lee, Johann Alsmeier, George Matamis
  • Patent number: 9305849
    Abstract: A monolithic three dimensional NAND string includes a semiconductor channel, an end part of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate, a charge storage material layer located between the plurality of control gate electrodes and the semiconductor channel, a tunnel dielectric located between the charge storage material layer and the semiconductor channel, and a blocking dielectric containing a plurality of clam-shaped portions each having two horizontal portions connected by a vertical portion. Each of the plurality of control gate electrodes are located at least partially in an opening in the clam-shaped blocking dielectric, and a plurality of discrete cover oxide segments embedded in part of a thickness of the charge storage material layer and located between the blocking dielectric and the charge storage material layer.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: April 5, 2016
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Masanori Tsutsumi, Shigehiro Fujino, Sateesh Koka, Senaka Kanakamedala, Yanli Zhang, Raghuveer S. Makala, Rahul Sharangpani, George Matamis, Wei Zhao
  • Publication number: 20160086969
    Abstract: A monolithic three dimensional NAND string includes a plurality of control gate electrodes extending substantially parallel to a major surface of a substrate in at least one active region, a plurality of semiconductor channels having at least one end portion of each of the plurality of semiconductor channels extending substantially perpendicular to the major surface of the substrate, at least one memory film located between each of the plurality of control gate electrodes and each respective semiconductor channel of the plurality of semiconductor channels, and at least one first slit trench extending substantially perpendicular to the major surface of the substrate. Each of the plurality of control gate electrodes has a nonlinear side wall adjacent to the at least one first slit trench in the at least one active region.
    Type: Application
    Filed: September 19, 2014
    Publication date: March 24, 2016
    Inventors: Yanli Zhang, Johann Alsmeier
  • Publication number: 20160086972
    Abstract: A vertically repeating stack of a unit layer stack is formed over a substrate. The unit layer stack includes a sacrificial material layer, a lower silicon oxide material layer, a first silicon oxide material layer, and an upper silicon oxide material layer. A memory opening can be formed through the vertically repeating stack, and a layer stack including a blocking dielectric layer, a memory material layer, a tunneling dielectric, and a semiconductor channel can be formed in the memory opening. The sacrificial material layers are replaced with electrically conductive layers. The first silicon oxide material layer can be removed to form backside recesses. Optionally, portions of the memory material layer can be removed to from discrete charge storage regions. The backside recesses can be filled with a low-k dielectric material and/or can include cavities within a dielectric material to provide reduced coupling between electrically conductive layers.
    Type: Application
    Filed: December 3, 2015
    Publication date: March 24, 2016
    Inventors: Yanli ZHANG, James KAI, Raghuveer S. MAKALA, Jin LIU, Murshed CHOWDHURY, Camilla HUANG, Johann ALSMEIER
  • Publication number: 20160071860
    Abstract: A memory device includes a plurality of memory cells arranged in a string substantially perpendicular to the major surface of the substrate in a plurality of device levels, at least one first select gate electrode located between the major surface of the substrate and the plurality of memory cells, at least one second select gate electrode located above the plurality of memory cells, a semiconductor channel having a portion that extends vertically along a direction perpendicular to the major surface, a first memory film contacting a first side of the semiconductor channel, and a second memory film contacting a second side of the semiconductor channel. The second memory film is electrically isolated from the first memory film, and is located at a same level as the first memory film.
    Type: Application
    Filed: June 24, 2015
    Publication date: March 10, 2016
    Inventors: James K. Kai, Yanli Zhang, Henry Chien, Johann Alsmeier
  • Publication number: 20160071861
    Abstract: A three dimensional NAND device includes a common vertical channel and electrically isolated control gate electrodes on different lateral sides of the channel in each device level to form different lateral portions of a memory cell in each device level. Dielectric separator structures are located between and electrically isolate the control gate electrodes. The lateral portions of the memory cell in each device level may be electrically isolated by at least one of doping ungated portions of the channel adjacent to the separator structures or storing electrons in the separator structure.
    Type: Application
    Filed: June 24, 2015
    Publication date: March 10, 2016
    Inventors: Andrey Serov, James K. Kai, Yanli Zhang, Henry Chien, Johann Alsmeier
  • Publication number: 20160064532
    Abstract: Methods of making a monolithic three dimensional NAND string that include forming a stack of alternating first material layers and second material layers over a substrate, where each of the second material layers includes a layer of a first silicon oxide material between two layers of a second silicon oxide material different from the first silicon oxide material, etching the stack to form a front side opening in the stack, forming a memory film over a sidewall of the front side opening, and forming a semiconductor channel in the front side opening such that at least a portion of the memory film is located between the semiconductor channel and the sidewall of the front side opening, where at least one of an air gap or a material which has a dielectric constant below 3.9 is formed between the respective two layers of second silicon oxide material.
    Type: Application
    Filed: August 26, 2014
    Publication date: March 3, 2016
    Inventors: Raghuveer S. MAKALA, Yanli ZHANG, Rahul SHARANGPANI, Yao-Sheng LEE, Senaka Krishna KANAKAMEDALA, George MATAMIS, Johann ALSMEIER
  • Publication number: 20160049421
    Abstract: A monolithic three dimensional NAND string includes a plurality of control gate electrodes extending substantially parallel to a major surface of a substrate, a memory opening extending substantially perpendicular to the major surface of the substrate and filled with a memory opening material including a memory film, and a dummy opening extending substantially perpendicular to the major surface of the substrate and filled with a dummy channel material which is different from the memory opening material. The dummy channel material has a higher Young's modulus than the memory opening material to offset warpage of the substrate due to the one of compressive and tensile stress imposed by the plurality of control gate electrodes on the substrate.
    Type: Application
    Filed: August 18, 2014
    Publication date: February 18, 2016
    Inventors: Yanli ZHANG, Raghuveer S. MAKALA, Johann ALSMEIER, Yao-Sheng LEE, Tiger XU
  • Patent number: 9240354
    Abstract: A semiconductor-on-insulator (SOI) substrate comprises a bulk semiconductor substrate, a buried insulator layer formed on the bulk substrate and an active semiconductor layer formed on the buried insulator layer. Impurities are implanted near the interface of the buried insulator layer and the active semiconductor layer. A diffusion barrier layer is formed between the impurities and an upper surface of the active semiconductor layer. The diffusion barrier layer prevents the impurities from diffusing therethrough.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: January 19, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Gregory G. Freeman, Kam Leung Lee, Chengwen Pei, Geng Wang, Yanli Zhang
  • Patent number: 9236396
    Abstract: A monolithic three dimensional NAND string includes a semiconductor channel, at least one end part of the semiconductor channel extending substantially perpendicular to a major surface of a substrate and a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate. The NAND string also includes a memory film located between the semiconductor channel and the plurality of control gate electrodes and a blocking dielectric containing a plurality of clam-shaped portions each having two horizontal portions connected by a vertical portion. The NAND string also includes a plurality of discrete cover silicon oxide segments located between the memory film and each respective clam-shaped portion of the blocking dielectric containing a respective control gate electrode. Each of the plurality of cover silicon oxide segments has curved upper and lower sides and substantially straight vertical sidewalls.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: January 12, 2016
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Sateesh Koka, Senaka Kanakamedala, Yanli Zhang, Raghuveer S. Makala, Rahul Sharangpani, George Matamis, Wei Zhao
  • Publication number: 20150380418
    Abstract: A NAND memory cell region of a NAND device includes a conductive source line that extends substantially parallel to a major surface of a substrate, a first semiconductor channel that extends substantially perpendicular to a major surface of the substrate, and a second semiconductor channel that extends substantially perpendicular to the major surface of the substrate. At least one of a bottom portion and a side portion of the first semiconductor channel contacts the conductive source line and at least one of a bottom portion and a side portion of the second semiconductor channel contacts the conductive source line.
    Type: Application
    Filed: June 27, 2014
    Publication date: December 31, 2015
    Inventors: Yanli Zhang, Go Shoji, Johann Alsmeier, Jayavel Pachamuthu, Yingda Dong, Jiahui Yuan
  • Publication number: 20150380424
    Abstract: A method of making a three dimensional NAND string includes providing a stack of alternating first material layers and second material layers over a substrate. The method further includes forming a front side opening in the stack, forming a tunnel dielectric in the front side opening, forming a semiconductor channel in the front side opening over the tunnel dielectric and forming a back side opening in the stack. The method also includes selectively removing the second material layers through the back side opening to form back side recesses between adjacent first material layers, forming a metal charge storage layer in the back side opening and in the back side recesses and forming discrete charge storage regions in the back side recesses by removing the metal charge storage layer from the back side opening and selectively recessing the metal charge storage layer in the back side recesses.
    Type: Application
    Filed: June 30, 2014
    Publication date: December 31, 2015
    Inventors: Raghuveer S. Makala, Yao-Sheng Lee, Senaka Krishna Kanakamedala, Yanli Zhang, George Matamis, Johann Alsmeier
  • Publication number: 20150380423
    Abstract: A method of making a monolithic three dimensional NAND string includes providing a first stack of alternating first material layers and second material layers over a major surface of a substrate. The first material layers include first silicon oxide layers, the second material layers include second silicon oxide layers, and the first silicon oxide layers have a different etch rate from the second silicon oxide when exposed to the same etching medium. The first stack includes a back side opening, a front side opening, and at least a portion of a floating gate layer, a tunnel dielectric and a semiconductor channel located in the front side opening. The method also includes selectively removing the first material layers through the back side opening to form back side control gate recesses between adjacent second material layers.
    Type: Application
    Filed: June 30, 2014
    Publication date: December 31, 2015
    Inventors: Senaka Krishna Kanakamedala, Yanli Zhang, Raghuveer S. Makala, Yao-Sheng Lee, Johann Alsmeier, George Matamis
  • Publication number: 20150357413
    Abstract: A monolithic three dimensional NAND string includes a semiconductor channel, where at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate, an interlevel insulating layer located between adjacent control gate electrodes, a blocking dielectric layer located in contact with the plurality of control gate electrodes and an interlevel insulating layer, a charge storage layer located at least partially in contact with the blocking dielectric layer, and a tunnel dielectric located between the charge storage layer and the semiconductor channel. The charge storage layer has a curved profile.
    Type: Application
    Filed: June 5, 2014
    Publication date: December 10, 2015
    Applicant: SanDisk Technologies Inc.
    Inventors: Yanli Zhang, Matthias Baenninger, Akira Matsudaira, Yao-Sheng Lee, Johann Alsmeier
  • Patent number: 9177966
    Abstract: A monolithic three dimensional NAND string device includes a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate in different device levels, a blocking dielectric located in contact with the plurality of control gate electrodes, at least one charge storage region located in contact with the blocking dielectric, and a tunnel dielectric located between the at least one charge storage region and the semiconductor channel. The semiconductor channel is a hollow body surrounding a middle region and at least one of an air gap or a low-k insulating material having a dielectric constant of less than 3.9 is located in the middle region.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: November 3, 2015
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Peter Rabkin, Wei Zhao, Yanli Zhang, Jayavel Pachamuthu
  • Patent number: 9159739
    Abstract: A monolithic three dimensional NAND string includes a semiconductor channel, with at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, and a plurality of copper containing control gate electrodes extending substantially parallel to the major surface of the substrate. The plurality of control gate electrodes include at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level. The NAND string also includes a blocking dielectric located over the plurality of control gates, a tunnel dielectric in contact with the semiconductor channel, and at least one charge storage region located between the blocking dielectric and the tunnel dielectric.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: October 13, 2015
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Raghuveer S. Makala, Yanli Zhang, Yao-Sheng Lee, Senaka Krishna Kanakamedala, Rahul Sharangpani, George Matamis, Johann Alsmeier, Seiji Shimabukuro, Genta Mizuno, Naoki Takeguchi
  • Patent number: 9099047
    Abstract: Some embodiments describe techniques that relate to power efficient, high frequency displays with motion blur mitigation. In one embodiment, the refresh rate of a display device may be dynamically modified, e.g., to reduce power consumption and/or reduce motion blur. Other embodiments are also described.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: August 4, 2015
    Assignee: Intel Corporation
    Inventors: Maximino Vasquez, Akihiro Takagi, Yanli Zhang, Achintya K. Bhowmik
  • Patent number: 9099202
    Abstract: Programming NAND strings in a 3D stacked storage device to a conductive state. Storage elements may be erased by raising their Vt and programmed by lowering their Vt. Programming may include applying a series of increasing voltages to selected bit lines until the selected memory cell is programmed. Unselected bit lines may be held at about ground, or close to ground. The selected word line may be grounded, or be held close to ground. Unselected word lines between the selected word line and the bit line may receive about the selected bit line voltage. Unselected word lines between the source line and the selected word line may receive about half the selected bit line voltage. Programming may be achieved without boosting channels of unselected NAND strings to inhibit them from programming. Therefore, program disturb associated with leakage of boosted channel potential may be avoided.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: August 4, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Andrei Mihnea, Xiying Costa, Yanli Zhang
  • Patent number: 9093466
    Abstract: A pair of horizontal-step-including trenches are formed in a semiconductor layer by forming a pair of first trenches having a first depth around a gate structure on the semiconductor layer, forming a disposable spacer around the gate structure to cover proximal portions of the first trenches, and by forming a pair of second trenches to a second depth greater than the first depth. The disposable spacer is removed, and selective epitaxy is performed to form an integrated epitaxial source and source extension region and an integrated epitaxial drain and drain extension region. A replacement gate structure can be formed after deposition and planarization of a planarization dielectric layer and subsequent removal of the gate structure and laterally expand the gate cavity over epitaxial source and drain extension regions. Alternately, a contact-level dielectric layer can be deposited directly on the integrated epitaxial regions and contact via structures can be formed therein.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: July 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Chengwen Pei, Geng Wang, Yanli Zhang
  • Patent number: 9076817
    Abstract: A pair of horizontal-step-including trenches are formed in a semiconductor layer by forming a pair of first trenches having a first depth around a gate structure on the semiconductor layer, forming a disposable spacer around the gate structure to cover proximal portions of the first trenches, and by forming a pair of second trenches to a second depth greater than the first depth. The disposable spacer is removed, and selective epitaxy is performed to form an integrated epitaxial source and source extension region and an integrated epitaxial drain and drain extension region. A replacement gate structure can be formed after deposition and planarization of a planarization dielectric layer and subsequent removal of the gate structure and laterally expand the gate cavity over expitaxial source and drain extension regions. Alternately, a contact-level dielectric layer can be deposited directly on the integrated epitaxial regions and contact via structures can be formed therein.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: July 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: Chengwen Pei, Geng Wang, Yanli Zhang