Patents by Inventor Yanli Zhang

Yanli Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10236300
    Abstract: A three-dimensional memory structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, an array of memory stack structures extending through the alternating stack, an array of drain select level assemblies overlying the alternating stack and having a same periodicity as the array of memory stack structures, drain select gate electrodes laterally surrounding respective rows of the drain select level assemblies, and a drain select level isolation strip located between a neighboring pair of drain select gate electrodes and including a pair of lengthwise sidewalls. Each of the pair of lengthwise sidewalls includes a laterally alternating sequence of planar sidewall portions and convex sidewall portions.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: March 19, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yanli Zhang, Masanori Tsutsumi, Shinsuke Yada, Sayako Nagamine, Johann Alsmeier
  • Patent number: 10224104
    Abstract: Two vertical NAND strings can share a common bit line by providing two pairs of drain select transistors. Channels of each vertical NAND string containing an adjoining pair of drain select transistors are incorporated into a respective vertical semiconductor channel, which is adjoined to a respective drain region which is connected to the common bit line. The drain select transistors have mismatched threshold voltages at each level such that each vertical NAND string includes a level at which a respective drain select transistor has a higher threshold voltage than a counterpart drain select transistor for the other vertical NAND string at the same level. By turning on three drain select transistors out of four, only one vertical NAND string can be activated while the common bit line is biased at a suitable bias voltage. A programming operation or a read operation can be performed only on the activated NAND string.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: March 5, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Murshed Chowdhury, Jin Liu, Yanli Zhang, Andrew Lin, Raghuveer S. Makala, Johann Alsmeier
  • Patent number: 10224407
    Abstract: A trench having a uniform depth is provided in an upper portion of a semiconductor substrate. A continuous dielectric material layer is formed, which includes a gate dielectric that fills an entire volume of the trench. A gate electrode is formed over the gate dielectric such that the gate electrode overlies a center portion of the gate dielectric and does not overlie a first peripheral portion and a second peripheral portion of the gate dielectric that are located on opposing sides of the center portion of the gate dielectric. After formation of a dielectric gate spacer, a source extension region and a drain extension region are formed within the semiconductor substrate by doping respective portions of the semiconductor substrate.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: March 5, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Murshed Chowdhury, Andrew Lin, James Kai, Yanli Zhang, Johann Alsmeier
  • Patent number: 10217746
    Abstract: A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a top surface of a substrate, such that each of the first insulating layers and the first electrically conductive layers includes a respective horizontally-extending portion and a respective non-horizontally-extending portion, memory stack structures extending through a memory array region of the first alternating stack that includes the horizontally-extending portions of the first electrically conductive layers, such that each of the memory stack structures comprises a memory film and a vertical semiconductor channel, a mesa structure located over the substrate, such that each respective non-horizontally-extending portion of the first insulating layers and the first electrically conductive layers is located over a sidewall of the mesa structure, and contact structures that contact a respective one of the non-horizontally-extending portions of the first electric
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: February 26, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Tae-Kyung Kim, Raghuveer S. Makala, Yanli Zhang, Hiroyuki Kinoshita, Daxin Mao, Jixin Yu, Yiyang Gong, Kazuto Watanabe, Michiaki Sano, Haruki Urata, Akira Takahashi
  • Publication number: 20190035803
    Abstract: A three-dimensional memory structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, an array of memory stack structures extending through the alternating stack, an array of drain select level assemblies overlying the alternating stack and having a same periodicity as the array of memory stack structures, drain select gate electrodes laterally surrounding respective rows of the drain select level assemblies, and a drain select level isolation strip located between a neighboring pair of drain select gate electrodes and including a pair of lengthwise sidewalls. Each of the pair of lengthwise sidewalls includes a laterally alternating sequence of planar sidewall portions and convex sidewall portions.
    Type: Application
    Filed: October 16, 2017
    Publication date: January 31, 2019
    Inventors: Yanli ZHANG, Masanori TSUTSUMI, Shinsuke YADA, Sayako NAGAMINE, Johann ALSMEIER
  • Patent number: 10192878
    Abstract: Sacrificial memory opening fill structures are formed through an alternating stack of insulating layers and sacrificial material layers. A drain select level isolation trench extending through drain select level sacrificial material layers is formed employing a combination of a photoresist layer including a linear opening and a pair of rows of sacrificial memory opening fill structures as an etch mask. Sacrificial spacers are formed on sidewalls of the drain select level isolation trench. A drain select level isolation dielectric structure is formed in a remaining volume of the drain select level isolation trench. The sacrificial memory opening fill structures are replaced with memory stack structures. The sacrificial material layers and the sacrificial spacers are replaced with a conductive material to form electrically conductive layers and conductive connector spacers.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: January 29, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Masanori Tsutsumi, Shinsuke Yada, Yanli Zhang
  • Publication number: 20180374866
    Abstract: A strap level sacrificial layer and an alternating stack of insulating layers and spacer material layers are formed over a substrate. An array of memory stack structures is formed through the alternating stack and the strap level sacrificial layer. Each memory film in the memory stack structures includes a metal oxide blocking dielectric. After formation of a source cavity by removal of the strap level sacrificial layer, an atomic layer etch process can be employed to remove portions of the metal oxide blocking dielectrics at the level of the source cavity. Outer sidewalls of semiconductor channels in the memory stack structures are exposed by additional etch processes, and a source strap layer is selectively deposited in the source cavity in contact with the semiconductor channel. If the spacer material layers are sacrificial material layers, all volumes of the sacrificial material layers can be replaced with the electrically conductive layers.
    Type: Application
    Filed: June 26, 2017
    Publication date: December 27, 2018
    Inventors: Raghuveer S. MAKALA, Senaka Krishna KANAKAMEDALA, Yanli ZHANG, Yao-Sheng LEE
  • Publication number: 20180366482
    Abstract: A three-dimensional memory device can be formed by first forming an alternating stack of insulating layers and stack level spacer material layers over a substrate. The stack level spacer material layers can be formed as, or are subsequently replaced with, stack level electrically conductive layers. A bottommost insulating spacer layer is formed with recesses that form grooves that are laterally spaced apart. Drain select level electrically conductive layers are formed over protruding portions and within the grooves of the bottommost insulating spacer layer by anisotropic deposition and isotropic etch back of a conductive material. Additional insulating spacer layers may be formed by anisotropic deposition of an insulating material. Additional drain select level electrically conductive layers can be formed by anisotropic deposition and isotropic etch back of additional conductive material.
    Type: Application
    Filed: June 20, 2017
    Publication date: December 20, 2018
    Inventors: Fei Zhou, Rahul Sharangpani, Yanli Zhang, Raghuveer S. Makala, Senaka Krishna Kanakamedala
  • Patent number: 10115730
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a semiconductor surface, a memory opening extending through the alternating stack, a semiconductor pedestal channel portion located at a bottom portion of the memory opening and contacting a top surface of the semiconductor surface, and a memory stack structure located in the memory opening and contacting a top surface of the pedestal channel portion. The memory stack structure includes a memory film and a vertical semiconductor channel located inside the memory film. A maximum lateral extent of the pedestal channel portion is greater than a maximum lateral dimension of an entire interface between the pedestal channel portion and the memory stack structure.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: October 30, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Ashish Baraskar, Naohiro Hosoda, Yanli Zhang, Raghuveer S. Makala, Hiroyuki Tanaka, Ryo Nakamura, Tadashi Nakamura
  • Patent number: 10115732
    Abstract: Discrete silicon nitride portions can be formed at each level of electrically conductive layers in an alternating stack of insulating layers and the electrically conductive layers. The discrete silicon nitride portions can be employed as charge trapping material portions, each of which is laterally contacted by a tunneling dielectric portion on the front side, and by a blocking dielectric portion on the back side. The tunneling dielectric portions may be formed as discrete material portions or portions within a tunneling dielectric layer. The blocking dielectric portions may be formed as discrete material portions or portions within a blocking dielectric layer. The discrete silicon nitride portions can be formed by depositing a charge trapping material layer and selectively removing portions of the charge trapping material layer at levels of the insulating layers. Various schemes may be employed to singulate the charge trapping material layer.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: October 30, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Jixin Yu, Zhenyu Lu, Daxin Mao, Yanli Zhang, Andrey Serov, Chun Ge, Johann Alsmeier
  • Patent number: 10103169
    Abstract: At least one alternating stack of insulating layers and silicon nitride layers is formed over a substrate. Memory stack structures are formed through the at least one alternating stack. A trench and an etch mask spacer are formed such that the trench extends through the entirety of the alternating stack while the etch mask covers upper layers of the at least one alternating stack. Lower silicon nitride layers are removed employing a first hot phosphoric acid wet etch process. After removal of the etch mask spacer, upper silicon nitride layers are removed employing a second hot phosphoric acid wet etch process. Electrically conductive layers are formed in the lateral recesses formed by removal of the silicon nitride layers.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: October 16, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Chun Ge, Fei Zhou, Yanli Zhang, Raghuveer S. Makala, Takashi Orimoto
  • Publication number: 20180286315
    Abstract: A dual scan out display system and method for performing the same are described. In one embodiment, the computing system comprises a display and a controller to provide data for separate portions of the display simultaneously using dual scanout.
    Type: Application
    Filed: March 28, 2017
    Publication date: October 4, 2018
    Inventors: Yanli Zhang, Srikanth Kambhatla
  • Publication number: 20180277046
    Abstract: In some examples, a display includes a plurality of display backlight groups, and one or more controller to determine one or more one-dimensional backlight group brightness level adjustments, to determine one or more two-dimensional backlight group brightness level adjustments, and to adjust a brightness of one or more of the backlight groups in response to content of a display image.
    Type: Application
    Filed: March 24, 2017
    Publication date: September 27, 2018
    Inventors: John Lang, Yunhui Chu, Yanli Zhang, Zhiming J. Zhuang
  • Patent number: 10083982
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, the alternating stack having a memory array region and a contact region containing stepped surfaces, and memory stack structures having a semiconductor channel and a memory film extending through the memory array region of the alternating stack. The electrically conductive layers include a drain select gate electrode and word lines, where the drain select gate electrode is thicker than each of the word lines.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: September 25, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Keisuke Shigemura, Junichi Ariyoshi, Masanori Tsutsumi, Michiaki Sano, Yanli Zhang, Raghuveer S. Makala
  • Patent number: 10074666
    Abstract: After formation of an alternating stack of insulating layers and sacrificial material layers, a memory opening can be formed through the alternating stack, which is subsequently filled with a columnar semiconductor pedestal portion and a memory stack structure. Breakage of the columnar semiconductor pedestal portion under mechanical stress can be avoided by growing a laterally protruding semiconductor portion by selective deposition of a semiconductor material after removal of the sacrificial material layers to form backside recesses. At least an outer portion of the laterally protruding semiconductor portion can be oxidized to form a tubular semiconductor oxide spacer. Electrically conductive layers can be formed in the backside recesses to provide word lines for a three-dimensional memory device.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: September 11, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Chun Ge, Yanli Zhang, Johann Alsmeier, Fabo Yu, Jixin Yu
  • Publication number: 20180248013
    Abstract: A trench having a uniform depth is provided in an upper portion of a semiconductor substrate. A continuous dielectric material layer is formed, which includes a gate dielectric that fills an entire volume of the trench. A gate electrode is formed over the gate dielectric such that the gate electrode overlies a center portion of the gate dielectric and does not overlie a first peripheral portion and a second peripheral portion of the gate dielectric that are located on opposing sides of the center portion of the gate dielectric. After formation of a dielectric gate spacer, a source extension region and a drain extension region are formed within the semiconductor substrate by doping respective portions of the semiconductor substrate.
    Type: Application
    Filed: February 28, 2017
    Publication date: August 30, 2018
    Inventors: Murshed CHOWDHURY, Andrew LIN, James KAI, Yanli ZHANG, Johann ALSMEIER
  • Publication number: 20180233513
    Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers. Vertical NAND strings are formed through the alternating stack, each of which includes a drain region, memory cell charge storage transistors, and a pair of drain select transistors in a series connection. A common bit line is electrically connected to drain regions of two vertical NAND strings. The drain select transistors of the two vertical NAND strings are configured such that drain select transistors sharing a first common drain select gate electrode provide a higher threshold voltage for one of the two vertical NAND strings, and drain select transistors sharing a second common drain select gate electrode provide a higher threshold voltage for the other of the two vertical NAND strings. The different threshold voltages can be provided by a combination of a masked ion implantation and selective charge injection.
    Type: Application
    Filed: April 9, 2018
    Publication date: August 16, 2018
    Inventors: Yanli Zhang, James Kai, Johann Alsmeier
  • Patent number: 10050054
    Abstract: A layer stack including an alternating stack of insulating layers and sacrificial material layers is formed over a substrate. After formation of memory stack structures, backside trenches are formed through the layer stack. The sacrificial material layers are replaced with electrically conductive layers. Drain select level dielectric isolation structures are formed through drain select level of the stack after formation of the electrically conductive layers. The drain select level dielectric isolation structures laterally separate portions of conductive layers that are employed as drain select level gate electrodes for the memory stack structures.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: August 14, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yanli Zhang, Johann Alsmeier, Raghuveer S. Makala, Senaka Kanakamedala, Rahul Sharangpani, James Kai
  • Publication number: 20180197876
    Abstract: After formation of an alternating stack of insulating layers and sacrificial material layers, a memory opening can be formed through the alternating stack, which is subsequently filled with a columnar semiconductor pedestal portion and a memory stack structure. Breakage of the columnar semiconductor pedestal portion under mechanical stress can be avoided by growing a laterally protruding semiconductor portion by selective deposition of a semiconductor material after removal of the sacrificial material layers to form backside recesses. At least an outer portion of the laterally protruding semiconductor portion can be oxidized to form a tubular semiconductor oxide spacer. Electrically conductive layers can be formed in the backside recesses to provide word lines for a three-dimensional memory device.
    Type: Application
    Filed: January 9, 2017
    Publication date: July 12, 2018
    Inventors: Chun GE, Yanli ZHANG, Johann ALSMEIER, Fabo YU, Jixin YU
  • Patent number: 10020314
    Abstract: Disclosed herein are methods of forming non-volatile storage. An opening may be etched through a stack of two alternating materials to a semiconductor substrate. A silicon nitride film may be formed on a vertical sidewall of the opening. The semiconductor substrate may be cleaned to remove oxide from the semiconductor substrate. The silicon nitride film protects the materials in the stack while cleaning the semiconductor substrate. The silicon nitride film may be converted to an oxide after cleaning the semiconductor substrate. A semiconductor region may be formed in contact with the cleaned semiconductor substrate. A memory cell film may be formed over the oxide in the opening. Control gates may be formed by replacing one of the materials in the stack with a conductive material. The oxide may serve as a blocking layer between the control gates and charge storage regions in the memory cell film.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: July 10, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Ashish Baraskar, Liang Pang, Yanli Zhang, Ching-Huang Lu, Yingda Dong