Patents by Inventor Yanli Zhang

Yanli Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10008570
    Abstract: The contact area between a source strap structure of a buried source layer and semiconductor channels within memory structures can be increased by laterally expanding a source-level volume in which the memory stack structures are formed. In one embodiment, sacrificial semiconductor pedestals can be formed in source-level memory openings prior to formation of a vertically alternating stack of insulating layers and sacrificial material layers. Memory openings can include bulging portions formed by removal of the sacrificial semiconductor pedestals. Memory stack structures can be formed with a greater sidewall surface area in the bulging portions to provide a greater contact area with the source strap structure. Alternatively, bottom portions of memory openings can be expanded selective to upper portions during, or after, formation of the memory openings to provide bulging portions and to increase the contact area with the source strap structure.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: June 26, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Jixin Yu, Kento Kitamura, Tong Zhang, Chun Ge, Yanli Zhang, Satoshi Shimizu, Yasuo Kasagi, Hiroyuki Ogawa, Daxin Mao, Kensuke Yamaguchi, Johann Alsmeier, James Kai
  • Publication number: 20180138193
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate and memory stack structures extending through the alternating stack. Each memory stack structure includes a memory film and a vertical semiconductor channel. An isolation trench laterally extends along a horizontal direction and divides at least two topmost electrically conductive layers. Two conductive rail structures are located on lengthwise sidewalls of the isolation trench and are electrically shorted to respective segments of the at least two topmost electrically conductive layers.
    Type: Application
    Filed: November 17, 2016
    Publication date: May 17, 2018
    Inventors: Yanli Zhang, Jin Liu, Raghuveer S. Makala, Murshed Chowdhury, Johann Alsmeier
  • Publication number: 20180138194
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, the alternating stack having a memory array region and a contact region containing stepped surfaces, and memory stack structures having a semiconductor channel and a memory film extending through the memory array region of the alternating stack. The electrically conductive layers include a drain select gate electrode and word lines, where the drain select gate electrode is thicker than each of the word lines.
    Type: Application
    Filed: April 25, 2017
    Publication date: May 17, 2018
    Inventors: Keisuke SHIGEMURA, Junichi ARIYOSHI, Masanori TSUTSUMI, Michiaki SANO, Yanli ZHANG, Raghuveer S. MAKALA
  • Patent number: 9972641
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate and memory stack structures extending through the alternating stack. Each memory stack structure includes a memory film and a vertical semiconductor channel. An isolation trench laterally extends along a horizontal direction and divides at least two topmost electrically conductive layers. Two conductive rail structures are located on lengthwise sidewalls of the isolation trench and are electrically shorted to respective segments of the at least two topmost electrically conductive layers.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: May 15, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yanli Zhang, Jin Liu, Raghuveer S. Makala, Murshed Chowdhury, Johann Alsmeier
  • Publication number: 20180122906
    Abstract: The contact area between a source strap structure of a buried source layer and semiconductor channels within memory structures can be increased by laterally expanding a source-level volume in which the memory stack structures are formed. In one embodiment, sacrificial semiconductor pedestals can be formed in source-level memory openings prior to formation of a vertically alternating stack of insulating layers and sacrificial material layers. Memory openings can include bulging portions formed by removal of the sacrificial semiconductor pedestals. Memory stack structures can be formed with a greater sidewall surface area in the bulging portions to provide a greater contact area with the source strap structure. Alternatively, bottom portions of memory openings can be expanded selective to upper portions during, or after, formation of the memory openings to provide bulging portions and to increase the contact area with the source strap structure.
    Type: Application
    Filed: March 14, 2017
    Publication date: May 3, 2018
    Inventors: Jixin YU, Kento KITAMURA, Tong ZHANG, Chun GE, Yanli ZHANG, Satoshi SHIMIZU, Yasuo KASAGI, Hiroyuki OGAWA, Daxin MAO, Kensuke YAMAGUCHI, Johann ALSMEIER, James KAI
  • Publication number: 20180122814
    Abstract: A three-dimensional non-volatile memory is provided with reduced programming variation across word lines. The gate lengths of word lines decrease from the top to the bottom of the memory hole. Increased programming speeds due to a narrow memory hole are offset by a smaller gate length at corresponding positions. A blocking dielectric thickness may also be varied, independently or in combination with a variable word line thickness. The blocking dielectric is formed with a horizontal thickness that is larger at regions adjacent to the lower word line layers and smaller at regions adjacent to the upper word line layers. The larger thickness at the lower word line layers reduces the programming speed in the memory hole for the lower word lines relative to the upper word lines. A variance in programming speed resulting from differences in memory hole diameter may be offset by a corresponding variance in blocking dielectric thickness.
    Type: Application
    Filed: December 19, 2017
    Publication date: May 3, 2018
    Applicant: SanDisk Technologies LLC
    Inventors: Ashish Baraskar, Liang Pang, Yanli Zhang, Raghuveer Makala, Yingda Dong
  • Patent number: 9960180
    Abstract: Memory openings can be formed through an alternating stack of insulating layers and sacrificial material layers. Memory stack structures including charge storage elements can be formed in the memory openings. Inter-level charge leakage in a three-dimensional memory device including a charge trapping layer can be minimized by employing a thin continuous charge trapping material layer within each memory opening. After removal of the sacrificial material layers and formation of backside recesses, discrete charge trapping material portions can be formed by selective growth of a charge trapping material from physically exposed surfaces of each thin continuous charge trapping material layer. The discrete charge trapping material portions can function as primary charge storage regions, and inter-level charge leakage can be minimized by the small thickness of the thin continuous charge trapping material layer.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: May 1, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Fei Zhou, Raghuveer Makala, Rahul Sharangpani, Keerti Shukla, Yanli Zhang, Peng Zhang
  • Publication number: 20180097009
    Abstract: A layer stack including an alternating stack of insulating layers and sacrificial material layers is formed over a substrate. After formation of memory stack structures, backside trenches are formed through the layer stack. The sacrificial material layers are replaced with electrically conductive layers. Drain select level dielectric isolation structures are formed through drain select level of the stack after formation of the electrically conductive layers. The drain select level dielectric isolation structures laterally separate portions of conductive layers that are employed as drain select level gate electrodes for the memory stack structures.
    Type: Application
    Filed: October 5, 2016
    Publication date: April 5, 2018
    Inventors: Yanli ZHANG, Johann ALSMEIER, Raghuveer S. MAKALA, Senaka KANAKAMEDALA, Rahul SHARANGPANI, James KAI
  • Patent number: 9917100
    Abstract: A three-dimensional memory device includes an alternating stack of electrically conductive layers and insulating layers located over a substrate, an array of memory stack structures. A source conductive line structure is provided between the substrate and the alternating stack. The source conductive line structure includes a plurality of parallel conductive rail structures extending along a same horizontal direction and adjoined to a common conductive straddling structure. Each memory stack structure straddles a vertical interface between a conductive rail structure and a support matrix. A semiconductor channel in each memory stack structure contacts a respective conductive rail structure and the support matrix.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: March 13, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Tong Zhang, Johann Alsmeier, James Kai, Jin Liu, Yanli Zhang
  • Patent number: 9888224
    Abstract: Systems, devices and methods are described including determining a display type and a display mode, preparing stereoscopic image content in response to the display mode, where preparing the stereoscopic image content includes storing a full resolution left image and a full resolution right image in memory, and determining a display refresh rate in response to at least a content frame rate of the stereoscopic image content. The stereoscopic image content may then be processed for display according to the display type, the display refresh rate, and a power policy.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: February 6, 2018
    Assignee: Intel Corporation
    Inventor: Yanli Zhang
  • Patent number: 9887207
    Abstract: A monolithic three dimensional NAND string includes a plurality of control gate electrodes extending substantially parallel to a major surface of a substrate, a memory opening extending substantially perpendicular to the major surface of the substrate and filled with a memory opening material including a memory film, and a dummy opening extending substantially perpendicular to the major surface of the substrate and filled with a dummy channel material which is different from the memory opening material. The dummy channel material has a higher Young's modulus than the memory opening material to offset warpage of the substrate due to the one of compressive and tensile stress imposed by the plurality of control gate electrodes on the substrate.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: February 6, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yanli Zhang, Raghuveer S. Makala, Johann Alsmeier, Yao-Sheng Lee, Tiger Xu
  • Publication number: 20180033794
    Abstract: A three-dimensional non-volatile memory is provided with reduced programming variation across word lines. The gate lengths of word lines decrease from the top to the bottom of the memory hole. Increased programming speeds due to a narrow memory hole are offset by a smaller gate length at corresponding positions. A blocking dielectric thickness may also be varied, independently or in combination with a variable word line thickness. The blocking dielectric is formed with a horizontal thickness that is larger at regions adjacent to the lower word line layers and smaller at regions adjacent to the upper word line layers. The larger thickness at the lower word line layers reduces the programming speed in the memory hole for the lower word lines relative to the upper word lines. A variance in programming speed resulting from differences in memory hole diameter may be offset by a corresponding variance in blocking dielectric thickness.
    Type: Application
    Filed: July 27, 2016
    Publication date: February 1, 2018
    Applicant: SanDisk Technologies LLC
    Inventors: Ashish Baraskar, Liang Pang, Yanli Zhang, Raghuveer Makala, Yingda Dong
  • Patent number: 9852677
    Abstract: Techniques related to image dithering are described herein. The techniques include receiving an image to be displayed at a display device and entering a content adaptive backlight control mode. The image is dithered during the content adaptive backlight control mode. The dithering is disabled during a panel self-refresh mode.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: December 26, 2017
    Assignee: Intel Corporation
    Inventors: Yanli Zhang, Seh Kwa
  • Publication number: 20170352678
    Abstract: Lower level metal interconnect structures are formed over a substrate with semiconductor devices thereupon. A semiconductor material layer and an alternating stack of spacer dielectric layers and insulating layers is formed over the lower level metal interconnect structures. An array of memory stack structures is formed through the alternating stack. Trenches are formed through the alternating stack such that a staircase region is located farther away from a threshold lateral distance from the trenches, while neighboring staircase regions are formed within the threshold lateral distance from the trenches. Portions of the spacer dielectric layers proximal to the trenches are replaced with electrically conductive layers, while a remaining portion of the alternating stack is present in the staircase region.
    Type: Application
    Filed: June 7, 2016
    Publication date: December 7, 2017
    Inventors: Zhenyu LU, Jixin YU, Johann ALSMEIER, Fumiaki TOYAMA, Yuki MIZUTANI, Hiroyuki OGAWA, Chun GE, Daxin MAO, Yanli ZHANG, Alexander CHU, Yan LI
  • Publication number: 20170352669
    Abstract: A memory stack structure including a memory film and a vertical semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulating layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulating layers, a backside blocking dielectric layer may be formed in the backside recesses and sidewalls of the memory stack structures. A metallic barrier material portion can be formed in each backside recess. A metallic material portion is formed on the metallic barrier material portion. Subsequently, a metal portion comprising a material selected from cobalt and ruthenium is formed directly on a sidewall of the metallic barrier material portion and a sidewall of the metallic material portion and an overlying insulating surface and an underlying insulating surface.
    Type: Application
    Filed: June 15, 2017
    Publication date: December 7, 2017
    Inventors: Rahul Sharangpani, Raghuveer Makala, Yanli Zhang, Yao-Sheng Lee
  • Patent number: 9831266
    Abstract: A three-dimensional memory device includes an alternating stack of electrically conductive layers and insulating layers located over a substrate, an array of memory stack structures. An alternating sequence of support pedestal structures and conductive rail structures extending along a same horizontal direction are provided between the substrate and the alternating stack. Each memory stack structure straddles a vertical interface between a conductive rail structure and a support pedestal structure. A semiconductor channel in each memory stack structure contacts a respective conductive rail structure, and is electrically isolated from an adjacent support pedestal structure by a portion of a memory film. The conductive rail structures can function as source regions of memory device.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: November 28, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: James Kai, Johann Alsmeier, Jin Liu, Yanli Zhang
  • Patent number: 9824966
    Abstract: A sacrificial film and an alternating stack of insulating layers and sacrificial material layers are sequentially formed over a substrate. A memory stack structure including a memory film and a vertical semiconductor channel is formed through the alternating stack and the sacrificial film on the substrate. A source level cavity is formed by introducing an etchant or a reactant through a backside trench and removing the sacrificial film. After removal of an annular portion of the memory film, a portion of the vertical semiconductor channel is converted into an annular source region by introducing electrical dopants into the channel. A source contact layer is formed in the source level cavity and directly on the annular source region. The sacrificial material layers are replaced with electrically conductive layers. The annular source region and the source contact layer can provide low source contact resistance in a three-dimensional NAND memory device.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: November 21, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Senaka Kanakamedala, Raghuveer S. Makala, Yanli Zhang, Rahul Sharangpani, James Kai, Yao-Sheng Lee
  • Patent number: 9812462
    Abstract: Techniques are provided for fabricating a memory device in which the memory cells have a uniform program and erase speed. In one aspect, a memory device is provided with memory holes having diameters which become progressively smaller as a distance between the memory holes and a local interconnect become progressively larger. In another aspect, a fabrication process is provided for such a memory device. The memory holes which are relatively closer to the local interconnect have a relatively thinner blocking oxide layer due to etching used to remove a sacrificial material of the control gate layers. The increased diameter compensates for the thinner blocking oxide layer.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: November 7, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Liang Pang, Ashish Baraskar, Yanli Zhang, Yingda Dong
  • Patent number: 9805662
    Abstract: A hybrid phase-in method mitigates the flicker and rolling artifact based on screen change detection or the combination of screen change detection and image spatial analysis. It applies, for example, to solutions that involve backlight and pixel modulation including global dimming and local dimming. If it is full screen change, then no phase-in is needed and the backlight and pixel change can be applied instantly. If it is partial screen change, then content type and spatial image analysis may be used to decide whether to use phase-in or not. The spatial image analysis concept provides additional useful information besides the image brightness analysis for display backlight power saving solutions to make better tradeoffs between power saving and visual quality.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: October 31, 2017
    Assignee: Intel Corporation
    Inventor: Yanli Zhang
  • Patent number: 9805805
    Abstract: A buried source semiconductor layer and p-doped semiconductor material portions are formed over a first portion of a substrate. The buried source semiconductor layer is an n-doped semiconductor material, and the p-doped semiconductor material portions are embedded within the buried source semiconductor layer. An alternating stack of insulating layers and spacer material layers is formed over the substrate. Memory stack structures are formed through the alternating stack. The spacer material layers are formed as, or are replaced with, electrically conductive layers. The buried source semiconductor layer may be formed prior to, or after, formation of the alternating stack. The buried source semiconductor layer underlies the alternating stack and overlies the first portion of the substrate, and contacts at least one surface of the vertical semiconductor channels. The p-doped semiconductor material portions contact at least one surface of a respective subset of the vertical semiconductor channels.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: October 31, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yanli Zhang, Johann Alsmeier, James Kai