Patents by Inventor Yanli Zhang

Yanli Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9806089
    Abstract: Metal floating gate electrodes can be formed for a three-dimensional memory device by forming a memory opening having lateral recesses at levels of spacer material layers between insulating layers, depositing a continuous metal layer, and inducing diffusion and agglomeration of the metal into the lateral recesses to form discrete metal portions employing an anneal process. The metallic material can migrate and form the discrete metal portions due to surface tension, which operates to minimize the surface area of the metallic material. Optionally, two or more continuous metal layers can be employed to form discrete metal portions including at least two metals. Optionally, a selective metal deposition process can be performed to deposit additional metal portions including a different metallic material on the discrete metal portions. The metal floating gate electrodes can be formed without employing an etch process. A tunneling dielectric layer and a semiconductor channel can be subsequently formed.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: October 31, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Somesh Peri, Raghuveer S. Makala, Yanli Zhang
  • Patent number: 9799670
    Abstract: A three-dimensional memory device includes an alternating stack of electrically conductive layers and insulating layers located over a substrate, an array of memory stack structures, each memory stack structure extending through the alternating stack and including a memory film and a semiconductor channel laterally surrounded by the memory film, and an array of dielectric pillars located between the alternating stack and the substrate.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: October 24, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Masatoshi Nishikawa, Jin Liu, Chun Ge, Yanli Zhang
  • Patent number: 9779948
    Abstract: Disclosed herein are methods of fabricating a source side select (SGS) transistor in 3D memory. The threshold voltage of the SGS transistor accurately meets a target threshold voltage. The SGS transistor has a semiconductor body that resides in a memory hole formed in a stack of alternating layers of two materials. During fabrication, a sacrificial layer may be removed to create recesses between dielectric layers in a stack. The sacrificial layer may be removed by introducing an etchant into slits formed in the stack. Thus, the recess may expose sidewalls of the body of the SGS transistor. An impurity may be introduced into this recess, by way of a slit, in order to dope the source side select transistor. This allows for precise control over the doping profile, which in turn provides for precise control over the threshold voltage of the SGS transistor.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: October 3, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Ashish Baraskar, Yanli Zhang, Ching-Huang Lu, Zhenyu Lu
  • Publication number: 20170278571
    Abstract: Two vertical NAND strings can share a common bit line by providing two pairs of drain select transistors. Channels of each vertical NAND string containing an adjoining pair of drain select transistors are incorporated into a respective vertical semiconductor channel, which is adjoined to a respective drain region which is connected to the common bit line. The drain select transistors have mismatched threshold voltages at each level such that each vertical NAND string includes a level at which a respective drain select transistor has a higher threshold voltage than a counterpart drain select transistor for the other vertical NAND string at the same level. By turning on three drain select transistors out of four, only one vertical NAND string can be activated while the common bit line is biased at a suitable bias voltage. A programming operation or a read operation can be performed only on the activated NAND string.
    Type: Application
    Filed: March 23, 2016
    Publication date: September 28, 2017
    Inventors: Murshed Chowdhury, Jin Liu, Yanli Zhang, Andrew Lin, Raghuveer S. Makala, Johann Alsmeier
  • Patent number: 9748267
    Abstract: A NAND memory cell region of a NAND device includes a conductive source line that extends substantially parallel to a major surface of a substrate, a first semiconductor channel that extends substantially perpendicular to a major surface of the substrate, and a second semiconductor channel that extends substantially perpendicular to the major surface of the substrate. At least one of a bottom portion and a side portion of the first semiconductor channel contacts the conductive source line and at least one of a bottom portion and a side portion of the second semiconductor channel contacts the conductive source line.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: August 29, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yanli Zhang, Go Shoji, Johann Alsmeier, Jayavel Pachamuthu, Yingda Dong, Jiahui Yuan
  • Patent number: 9748266
    Abstract: A gate dielectric layer including a tunneling gate dielectric layer, a charge trapping gate dielectric layer, and a cap gate dielectric layer is formed on a horizontal semiconductor channel. An alternating stack of insulating layers and spacer material layers is formed over the gate dielectric layer. The spacer material layers are formed as, or are subsequently replaced with, electrically conducive layers. Memory stack structures are formed through the alternating stack and the gate dielectric layer. Electrical charges can be injected into the charge trapping gate dielectric layer from the horizontal semiconductor channel to program the threshold voltage of a select field effect transistor employing a bottommost electrically conductive layer as a select gate electrode. The programmable threshold voltage can be advantageously employed to provide enhanced electrical isolation among word lines.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: August 29, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Ashish Baraskar, Yanli Zhang, Liang Pang, Ching-Huang Lu, Matthias Baenninger, Yingda Dong
  • Publication number: 20170243879
    Abstract: Discrete silicon nitride portions can be formed at each level of electrically conductive layers in an alternating stack of insulating layers and the electrically conductive layers. The discrete silicon nitride portions can be employed as charge trapping material portions, each of which is laterally contacted by a tunneling dielectric portion on the front side, and by a blocking dielectric portion on the back side. The tunneling dielectric portions may be formed as discrete material portions or portions within a tunneling dielectric layer. The blocking dielectric portions may be formed as discrete material portions or portions within a blocking dielectric layer. The discrete silicon nitride portions can be formed by depositing a charge trapping material layer and selectively removing portions of the charge trapping material layer at levels of the insulating layers. Various schemes may be employed to singulate the charge trapping material layer.
    Type: Application
    Filed: February 22, 2016
    Publication date: August 24, 2017
    Inventors: Jixin YU, Zhenyu LU, Daxin MAO, Yanli ZHANG, Andrey SEROV, Chun GE, Johann ALSMEIER
  • Patent number: 9736443
    Abstract: Content adaptive power management technologies of projector systems are described. One method analyzes image data to be displayed by a projector system. A projector brightness of a light source of the projector system is adjusted based on the analyzed image data. The pixel values of the image data input into an imager of the projector system are adjusted based on the analyzed image data.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: August 15, 2017
    Assignee: Intel Corporation
    Inventor: Yanli Zhang
  • Patent number: 9728546
    Abstract: A three dimensional NAND device includes a common vertical channel and electrically isolated control gate electrodes on different lateral sides of the channel in each device level to form different lateral portions of a memory cell in each device level. Dielectric separator structures are located between and electrically isolate the control gate electrodes. The lateral portions of the memory cell in each device level may be electrically isolated by at least one of doping ungated portions of the channel adjacent to the separator structures or storing electrons in the separator structure.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: August 8, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Andrey Serov, James K. Kai, Yanli Zhang, Henry Chien, Johann Alsmeier
  • Patent number: 9698153
    Abstract: Alignment between memory openings through multiple tier structures can be facilitated employing a temporary landing pad. The temporary landing pad can have a greater area than the horizontal cross-sectional area of a first memory opening through a first tier structure including a first alternating stack of first insulating layers and first spacer material layers. An upper portion of a first memory film is removed, and a sidewall of an insulating cap layer that defines the first memory opening can be laterally recessed to form a recessed cavity. A sacrificial fill material is deposited in the recessed cavity to form a sacrificial fill material portion, which functions as the temporary landing pad for a second memory opening that is subsequently formed through a second tier structure including second insulating layers and second spacer material layers. A memory stack structure can be formed through the first and second tier structures.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: July 4, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Jin Liu, Yanli Zhang, Murshed Chowdhury, Raghuveer S. Makala, Johann Alsmeier
  • Patent number: 9691884
    Abstract: Methods of making a monolithic three dimensional NAND string that include forming a stack of alternating first material layers and second material layers over a substrate, where each of the second material layers includes a layer of a first silicon oxide material between two layers of a second silicon oxide material different from the first silicon oxide material, etching the stack to form a front side opening in the stack, forming a memory film over a sidewall of the front side opening, and forming a semiconductor channel in the front side opening such that at least a portion of the memory film is located between the semiconductor channel and the sidewall of the front side opening, where at least one of an air gap or a material which has a dielectric constant below 3.9 is formed between the respective two layers of second silicon oxide material.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: June 27, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Raghuveer S. Makala, Yanli Zhang, Rahul Sharangpani, Yao-Sheng Lee, Senaka Krishna Kanakamedala, George Matamis, Johann Alsmeier
  • Patent number: 9672917
    Abstract: Systems and methods for implementing and using stacked vertical memory array architectures. A first NAND string may be formed or arranged above a second NAND string. The first NAND string may include a first drain-side select gate connected to a first set of memory cell transistors connected to a first source-side select gate. The second NAND string may include a second drain-side select gate connected to a second set of memory cell transistors connected to a second source-side select gate. The first NAND string and the second NAND string may comprise portions of the same or different memory array architectures (e.g., the first NAND string may be part of a memory array that uses U-shaped NAND strings and the second NAND string may be part of a memory array that uses single vertical NAND strings).
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: June 6, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Xiying Costa, Henry Chien, Yao-Sheng Lee, Yanli Zhang
  • Patent number: 9673213
    Abstract: A method of manufacturing a structure includes forming an in-process alternating stack including insulating layers and spacer material layers over a substrate, forming two sets of stepped surfaces by dividing the in-process alternating stack into a first alternating stack and a second alternating stack, the first alternating stack having first stepped surfaces and the second alternating stack having second stepped surfaces, forming at least one memory stack structure through the first alternating stack, each of the at least one memory stack structure including charge storage regions, a tunneling dielectric, and a semiconductor channel, replacing portions of the insulating layers in the first alternating stack with electrically conductive layers while leaving intact portions of the insulating layers in the second alternating stack, and forming a contact via structure through the second alternating stack to contact a peripheral semiconductor device under the second stack.
    Type: Grant
    Filed: February 15, 2016
    Date of Patent: June 6, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Jixin Yu, Yanli Zhang, Zhenyu Lu, Johann Alsmeier, Daxin Mao
  • Patent number: 9672916
    Abstract: Methods for performing memory operations on a memory array that includes inverted NAND strings are described. The memory operations may include erase operations, read operations, programming operations, program verify operations, and erase verify operations. An inverted NAND string may include a string of inverted floating gate transistors or a string of inverted charge trap transistors. In one embodiment, an inverted floating gate transistor may include a tunneling layer between a floating gate of the inverted floating gate transistor and a control gate of the inverted floating gate transistor. The arrangement of the tunneling layer between the floating gate and the control gate allows electrons to be added to or removed from the floating gate via F-N tunneling between the floating gate and the control gate. The inverted NAND string may be formed above a substrate and oriented such that the inverted NAND string is orthogonal to the substrate.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: June 6, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yanli Zhang, George Samachisa, Johann Alsmeier, Jian Chen
  • Publication number: 20170148810
    Abstract: A three-dimensional memory device includes an alternating stack of electrically conductive layers and insulating layers located over a substrate, an array of memory stack structures. An alternating sequence of support pedestal structures and conductive rail structures extending along a same horizontal direction are provided between the substrate and the alternating stack. Each memory stack structure straddles a vertical interface between a conductive rail structure and a support pedestal structure. A semiconductor channel in each memory stack structure contacts a respective conductive rail structure, and is electrically isolated from an adjacent support pedestal structure by a portion of a memory film. The conductive rail structures can function as source regions of memory device.
    Type: Application
    Filed: August 1, 2016
    Publication date: May 25, 2017
    Inventors: James Kai, Johann Alsmeier, Jin Liu, Yanli Zhang
  • Publication number: 20170148811
    Abstract: A three-dimensional memory device includes an alternating stack of electrically conductive layers and insulating layers located over a substrate, an array of memory stack structures. A source conductive line structure is provided between the substrate and the alternating stack. The source conductive line structure includes a plurality of parallel conductive rail structures extending along a same horizontal direction and adjoined to a common conductive straddling structure. Each memory stack structure straddles a vertical interface between a conductive rail structure and a support matrix. A semiconductor channel in each memory stack structure contacts a respective conductive rail structure and the support matrix.
    Type: Application
    Filed: November 17, 2016
    Publication date: May 25, 2017
    Inventors: Tong ZHANG, Johann ALSMEIER, James KAI, Jin LIU, Yanli ZHANG
  • Publication number: 20170148800
    Abstract: A three-dimensional memory device includes an alternating stack of electrically conductive layers and insulating layers located over a substrate, an array of memory stack structures, each memory stack structure extending through the alternating stack and including a memory film and a semiconductor channel laterally surrounded by the memory film, and an array of dielectric pillars located between the alternating stack and the substrate.
    Type: Application
    Filed: February 8, 2016
    Publication date: May 25, 2017
    Inventors: Masatoshi NISHIKAWA, Jin LIU, Chun GE, Yanli ZHANG
  • Patent number: 9646990
    Abstract: Methods of making monolithic three-dimensional memory devices include performing a first etch to form a memory opening and a second etch using a different etching process to remove a damaged portion of the semiconductor substrate from the bottom of the memory opening. A single crystal semiconductor material is formed over the substrate in the memory opening using an epitaxial growth process. Additional embodiments include improving the quality of the interface between the semiconductor channel material and the underlying semiconductor layers in the memory opening which may be damaged by the bottom opening etch, including forming single crystal semiconductor channel material by epitaxial growth from the bottom surface of the memory opening and/or oxidizing surfaces exposed to the bottom opening etch and removing the oxidized surfaces prior to forming the channel material. Monolithic three-dimensional memory devices formed by the embodiment methods are also disclosed.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: May 9, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Sateesh Koka, Raghuveer S. Makala, Yanli Zhang, Senaka Kanakamedala, Rahul Sharangpani, Yao-Sheng Lee, George Matamis
  • Patent number: 9627399
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed on a substrate. Separator insulator structures can be optionally formed through the alternating stack. Memory opening are formed through the alternating stack, and the sacrificial material layers are removed selective to the insulating layers. Electrically conductive layers are formed in the lateral recesses by deposition of at least one conductive material. Metal-semiconductor alloy regions are appended to the electrically conductive layers by depositing at least a semiconductor material and inducing reaction of the semiconductor material with the material of the electrically conductive layers and/or a sacrificial metal layer. Memory stack structures can be formed in the memory openings and directly on the metal-semiconductor alloy regions of the electrically conductive layers.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: April 18, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Senaka Kanakamedala, Raghuveer S. Makala, Yanli Zhang, Yao-Sheng Lee, George Matamis
  • Patent number: 9627395
    Abstract: A stack including an alternating plurality of first material layers and second material layers is provided. A memory opening is formed and at least a contiguous semiconductor material portion including a semiconductor channel is formed therein. The contiguous semiconductor material portion includes an amorphous or polycrystalline semiconductor material. A metallic material portion is provided at a bottom surface of the semiconductor channel, at a top surface of the semiconductor channel, or on portions of an outer sidewall surface of the semiconductor channel. An anneal is performed to induce diffusion of a metal from the metallic material portion through the semiconductor channel, thereby inducing conversion of the amorphous or polycrystalline semiconductor material into a crystalline semiconductor material. The crystalline semiconductor material has a relatively large grain size due to the catalytic crystallization process, and can provide enhanced charge carrier mobility.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: April 18, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yanli Zhang, Raghuveer S. Makala, Johann Alsmeier