Abstract: Quantum device, including: a semiconductor portion comprising several first quantum dot regions each disposed between at least two second tunnel barrier regions and placed next to the two second regions; first gates each comprising a first conductive portion; second gates each comprising at least a second conductive portion and a second dielectric disposed between the second conductive portion and the first conductive portion of one of the first gates, such that each of the first gates is disposed between the semi-conductor portion and one of the second gates; wherein the first and second gates are disposed above the first regions or above the second regions, the second gates being solely located in a vertical extension of the first gates.

Abstract: A spin qubit quantum device, comprising: a semiconductor portion comprising a first region disposed between two second regions; a first control gate disposed in direct contact with the first region and configured to control a minimum potential energy level in the first region, and disposed in direct contact with a first face of the semiconductor portion; and second electrostatic control gates, each disposed in direct contact with one of the second regions and configured to control a maximum potential energy level in one of the second regions, and disposed in direct contact with a second face, opposite to the first face, of the semiconductor portion, and wherein the first gate is not aligned with the second gates.

Abstract: A method is described for controlling a spin qubit quantum device that includes a semiconducting portion, a dielectric layer covered by the semiconducting portion, a front gate partially covering an upper edge of the semiconducting portion, and a back gate. The method includes, during a manipulation of a spin state, the exposure of the device to a magnetic field B of value such that g·?B·B>min(?(Vbg)). The method also includes the application, on the rear gate, of an electrical potential Vbg of value such that ?(Vbg)<g·?B·B+2|MSO|, and the application, on the front gate, of a confinement potential and an RF electrical signal triggering a change of spin state, with g corresponding to the Landé factor, ?B corresponding to a Bohr magneton, ? corresponding to an intervalley energy difference in the semiconducting portion, and MSO corresponding to the intervalley spin-orbit coupling.

Abstract: A method is described for controlling a spin qubit quantum device that includes a semiconducting portion, a dielectric layer covered by the semiconducting portion, a front gate partially covering an upper edge of the semiconducting portion, and a back gate. The method includes, during a manipulation of a spin state, the exposure of the device to a magnetic field B of value such that g·?B·B>min(?(Vbg)). The method also includes the application, on the rear gate, of an electrical potential Vbg of value such that ?(Vbg)<g·?B·B+2|MSO|, and the application, on the front gate, of a confinement potential and an RF electrical signal triggering a change of spin state, with g corresponding to the Landé factor, ?B corresponding to a Bohr magneton, ? corresponding to an intervalley energy difference in the semiconducting portion, and MSO corresponding to the intervalley spin-orbit coupling.

Abstract: Single-electron transistor comprising at least: first semiconductor portions forming source and drain regions, a second semiconductor portion forming at least one quantum island, third semiconductor portions forming tunnel junctions between the second semiconductor portion and the first semiconductor portions, a gate and a gate dielectric located on at least the second semiconductor portion, in which a thickness of each of the first semiconductor portions is greater than the thickness of the second semiconductor portion, and in which a thickness of the second semiconductor portion is greater than the thickness of each of the third semiconductor portions.

Abstract: Single-electron transistor comprising at least: first semiconductor portions forming source and drain regions, a second semiconductor portion forming at least one quantum island, third semiconductor portions forming tunnel junctions between the second semiconductor portion and the first semiconductor portions, a gate and a gate dielectric located on at least the second semiconductor portion, in which a thickness of each of the first semiconductor portions is greater than the thickness of the second semiconductor portion, and in which a thickness of the second semiconductor portion is greater than the thickness of each of the third semiconductor portions.