Patents by Inventor Yanning Sun
Yanning Sun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9508640Abstract: A method for forming a device with a multi-tiered contact structure includes forming first contacts in via holes down to a first level, forming a dielectric capping layer over exposed portions of the first contacts and forming a dielectric layer over the capping layer. Via holes are opened in the dielectric layer down to the capping layer. Holes are opened in the capping layer through the via holes to expose the first contacts. Contact connectors and second contacts are formed in the via holes such that the first and second contacts are connected through the capping layer by the contact connectors to form multi-tiered contacts.Type: GrantFiled: July 12, 2013Date of Patent: November 29, 2016Assignee: GlobalFoundries, Inc.Inventors: Cheng-Wei Cheng, Szu-Lin Cheng, Keith E. Fogel, Edward W. Kiewra, Amlan Majumdar, Devendra K. Sadana, Kuen-Ting Shiu, Yanning Sun
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Publication number: 20160322223Abstract: A method of forming a semiconducting material includes depositing a graded buffer on a substrate to form a graded layer of an indium (In) containing III-V material, the In containing III-V material being indium-gallium-arsenic (InGaAs) or indium-aluminum-arsenic (InAlAs) and comprising In in an increasing atomic gradient up to 35 atomic % (at. %) based on total atomic weight of InGa or InAl; and forming a layer of InGaAs on the graded layer, the layer of InGaAs comprising about 25 to about 100 at. % In based on total atomic weight of InGa.Type: ApplicationFiled: June 19, 2015Publication date: November 3, 2016Inventors: Cheng-Wei Cheng, Devendra K. Sadana, Keun-Ting Shiu, Yanning Sun
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Publication number: 20160322222Abstract: A method of forming a semiconducting material includes depositing a graded buffer on a substrate to form a graded layer of an indium (In) containing III-V material, the In containing III-V material being indium-gallium-arsenic (InGaAs) or indium-aluminum-arsenic (InAlAs) and comprising In in an increasing atomic gradient up to 35 atomic % (at. %) based on total atomic weight of InGa or InAl; and forming a layer of InGaAs on the graded layer, the layer of InGaAs comprising about 25 to about 100 at. % In based on total atomic weight of InGa.Type: ApplicationFiled: April 28, 2015Publication date: November 3, 2016Inventors: Cheng-Wei Cheng, Devendra K. Sadana, Keun-Ting Shiu, Yanning Sun
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Patent number: 9437614Abstract: A method of forming an active device on a semiconductor wafer includes the steps of: forming a plurality of semiconductor fins on at least a portion of a semiconductor substrate; forming a dielectric layer on at least a portion of the semiconductor substrate, the dielectric layer filling gaps between adjacent fins; forming a plurality of gate structures on an upper surface of the dielectric layer; forming a channel region on the dielectric layer and under at least a portion of the gate structures, the channel region comprising a first crystalline semiconductor material; forming source and drain epitaxy regions on an upper surface of the dielectric layer and between adjacent gate structures, the source and rain regions being spaced laterally from one another; and replacing the channel region with a second crystalline semiconductor material after high-temperature processing used in fabricating the active device has been completed.Type: GrantFiled: September 18, 2015Date of Patent: September 6, 2016Assignee: International Business Machines CorporationInventors: Sanghoon Lee, Effendi Leobandung, Renee T. Mo, Yanning Sun
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Publication number: 20160254193Abstract: A method for fabricating a semiconductor device may include receiving a gated substrate comprising a substrate with a channel layer and a gate structure formed thereon, over-etching the channel layer to expose an extension region below the gate structure, epitaxially growing a halo layer on the exposed extension region using a first in-situ dopant and epitaxially growing a source or drain on the halo layer using a second in-situ dopant, wherein the first in-situ dopant and the second in-situ dopant are of opposite doping polarity. Using an opposite doping polarity may provide an energy band barrier for the semiconductor device and reduce leakage current. A corresponding apparatus is also disclosed herein.Type: ApplicationFiled: April 7, 2016Publication date: September 1, 2016Inventors: Cheng-Wei Cheng, Pranita Kerber, Young-Hee Kim, Effendi Leobandung, Yanning Sun
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Publication number: 20160254352Abstract: A method for fabricating a semiconductor device may include receiving a gated substrate comprising a substrate with a channel layer and a gate structure formed thereon, over-etching the channel layer to expose an extension region below the gate structure, epitaxially growing a halo layer on the exposed extension region using a first in-situ dopant and epitaxially growing a source or drain on the halo layer using a second in-situ dopant, wherein the first in-situ dopant and the second in-situ dopant are of opposite doping polarity. Using an opposite doping polarity may provide an energy band barrier for the semiconductor device and reduce leakage current. A corresponding apparatus is also disclosed herein.Type: ApplicationFiled: May 4, 2016Publication date: September 1, 2016Inventors: Cheng-Wei Cheng, Pranita Kerber, Young-Hee Kim, Effendi Leobandung, Yanning Sun
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Patent number: 9397161Abstract: A method for fabricating a semiconductor device may include receiving a gated substrate comprising a substrate with a channel layer and a gate structure formed thereon, over-etching the channel layer to expose an extension region below the gate structure, epitaxially growing a halo layer on the exposed extension region using a first in-situ dopant and epitaxially growing a source or drain on the halo layer using a second in-situ dopant, wherein the first in-situ dopant and the second in-situ dopant are of opposite doping polarity. Using an opposite doping polarity may provide an energy band barrier for the semiconductor device and reduce leakage current. A corresponding apparatus is also disclosed herein.Type: GrantFiled: February 26, 2015Date of Patent: July 19, 2016Assignee: International Business Machines CorporationInventors: Cheng-Wei Cheng, Pranita Kerber, Young-Hee Kim, Effendi Leobandung, Yanning Sun
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Publication number: 20160172465Abstract: A method of forming a semiconductor substrate including a type III-V semiconductor material directly on a dielectric material that includes forming a trench in a dielectric layer, and forming a via within the trench extending from a base of the trench to an exposed upper surface of an underlying semiconductor including substrate. A III-V semiconductor material is formed extending from the exposed upper surface of the semiconductor substrate filling at least a portion of the trench.Type: ApplicationFiled: February 19, 2016Publication date: June 16, 2016Inventors: Cheng-Wei Cheng, Edward W. Kiewra, Amlan Majumdar, Uzma Rana, Devendra K. Sadana, Kuen-Ting Shiu, Yanning Sun
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Patent number: 9337281Abstract: A semiconductor structure includes a III-V monocrystalline layer and a germanium surface layer. An interlayer is formed directly between the III-V monocrystalline layer and the germanium surface layer from a material selected to provide stronger nucleation bonding between the interlayer and the germanium surface layer than nucleation bonding that would be achievable directly between the III-V monocrystalline layer and the germanium surface layer such that a continuous, relatively defect-free germanium surface layer is provided.Type: GrantFiled: July 20, 2015Date of Patent: May 10, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Cheng-Wei Cheng, Jack O. Chu, Devendra K. Sadana, Kuen-Ting Shiu, Yanning Sun
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Patent number: 9324853Abstract: A method including forming a pair of inner spacers along a vertical sidewall of a gate trench, gate trench extending into a III-V compound semiconductor-containing heterostructure, forming a gate conductor within the gate trench, removing a portion of a first dielectric layer selective to the gate conductor and the pair of inner spacers, forming a pair of outer spacers adjacent to the pair of inner spacers, the outer spacers are in direct contact with and self-aligned to the inner spacers, and forming a pair of source-drain contacts within an uppermost layer of the III-V compound semiconductor-containing heterostructure, the pair of source-drain contacts are self-aligned to the pair of outer spacers such that an edge of each individual source-drain contact is aligned with an outside edge of each individual outer spacer.Type: GrantFiled: July 8, 2015Date of Patent: April 26, 2016Assignee: International Business Machines CorporationInventors: Anirban Basu, Amlan Majumdar, Kuen-Ting Shiu, Yanning Sun
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Patent number: 9287115Abstract: A method of forming a semiconductor substrate including a type III-V semiconductor material directly on a dielectric material that includes forming a trench in a dielectric layer, and forming a via within the trench extending from a base of the trench to an exposed upper surface of an underlying semiconductor including substrate. A III-V semiconductor material is formed extending from the exposed upper surface of the semiconductor substrate filling at least a portion of the trench.Type: GrantFiled: March 12, 2014Date of Patent: March 15, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cheng-Wei Cheng, Edward W. Kiewra, Amlan Majumdar, Uzma Rana, Devendra K. Sadana, Kuen-Ting Shiu, Yanning Sun
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Publication number: 20160071968Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a replacement channel composed of a III-V compound semiconductor material in a doped layer of a III-V compound semiconductor substrate. The replacement channel may be formed by removing a portion of the doped layer located directly below a dummy gate stack that has been removed. A III-V compound semiconductor material may be grown in the removed the portion to form the replacement channel and a gate stack may be formed on the replacement channel.Type: ApplicationFiled: September 8, 2014Publication date: March 10, 2016Inventors: Effendi Leobandung, Yanning Sun
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Publication number: 20150325682Abstract: A semiconductor structure includes a III-V monocrystalline layer and a germanium surface layer. An interlayer is formed directly between the III-V monocrystalline layer and the germanium surface layer from a material selected to provide stronger nucleation bonding between the interlayer and the germanium surface layer than nucleation bonding that would be achievable directly between the III-V monocrystalline layer and the germanium surface layer such that a continuous, relatively defect-free germanium surface layer is provided.Type: ApplicationFiled: July 20, 2015Publication date: November 12, 2015Inventors: CHENG-WEI CHENG, JACK O. CHU, DEVENDRA K. SADANA, KUEN-TING SHIU, YANNING SUN
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Publication number: 20150325650Abstract: A method including forming a pair of inner spacers along a vertical sidewall of a gate trench, gate trench extending into a III-V compound semiconductor-containing heterostructure, forming a gate conductor within the gate trench, removing a portion of a first dielectric layer selective to the gate conductor and the pair of inner spacers, forming a pair of outer spacers adjacent to the pair of inner spacers, the outer spacers are in direct contact with and self-aligned to the inner spacers, and forming a pair of source-drain contacts within an uppermost layer of the III-V compound semiconductor-containing heterostructure, the pair of source-drain contacts are self-aligned to the pair of outer spacers such that an edge of each individual source-drain contact is aligned with an outside edge of each individual outer spacer.Type: ApplicationFiled: July 8, 2015Publication date: November 12, 2015Inventors: Anirban Basu, Amlan Majumdar, Kuen-Ting Shiu, Yanning Sun
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Patent number: 9159822Abstract: A method including forming a pair of inner spacers along a vertical sidewall of a gate trench, gate trench extending into a III-V compound semiconductor-containing heterostructure, forming a gate conductor within the gate trench, removing a portion of a first dielectric layer selective to the gate conductor and the pair of inner spacers, forming a pair of outer spacers adjacent to the pair of inner spacers, the outer spacers are in direct contact with and self-aligned to the inner spacers, and forming a pair of source-drain contacts within an uppermost layer of the III-V compound semiconductor-containing heterostructure, the pair of source-drain contacts are self-aligned to the pair of outer spacers such that an edge of each individual source-drain contact is aligned with an outside edge of each individual outer spacer.Type: GrantFiled: February 24, 2014Date of Patent: October 13, 2015Assignee: International Business Machines CorporationInventors: Anirban Basu, Amlan Majumdar, Kuen-Ting Shiu, Yanning Sun
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Publication number: 20150262818Abstract: A method of forming a semiconductor substrate including a type III-V semiconductor material directly on a dielectric material that includes forming a trench in a dielectric layer, and forming a via within the trench extending from a base of the trench to an exposed upper surface of an underlying semiconductor including substrate. A III-V semiconductor material is formed extending from the exposed upper surface of the semiconductor substrate filling at least a portion of the trench.Type: ApplicationFiled: March 12, 2014Publication date: September 17, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cheng-Wei Cheng, Edward W. Kiewra, Amlan Majumdar, Uzma Rana, Devendra K. Sadana, Kuen-Ting Shiu, Yanning Sun
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Publication number: 20150255281Abstract: A method for forming a crystalline compound material on a single element substrate includes etching a high aspect ratio trench in a single element crystalline substrate and forming a dielectric layer over the substrate and on sidewalls and a bottom of the trench. The dielectric is removed from the bottom of the trench to expose the substrate at the bottom of the trench. A crystalline compound material is selectively grown on the substrate at the bottom of the trench.Type: ApplicationFiled: May 22, 2015Publication date: September 10, 2015Inventors: Robert L. Bruce, Cheng-Wei Cheng, Joel P. de Souza, Ryan M. Martin, Uzma Rana, Devendra K. Sadana, Kuen-Ting Shiu, Yanning Sun
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Publication number: 20150243773Abstract: A method including forming a pair of inner spacers along a vertical sidewall of a gate trench, gate trench extending into a III-V compound semiconductor-containing heterostructure, forming a gate conductor within the gate trench, removing a portion of a first dielectric layer selective to the gate conductor and the pair of inner spacers, forming a pair of outer spacers adjacent to the pair of inner spacers, the outer spacers are in direct contact with and self-aligned to the inner spacers, and forming a pair of source-drain contacts within an uppermost layer of the III-V compound semiconductor-containing heterostructure, the pair of source-drain contacts are self-aligned to the pair of outer spacers such that an edge of each individual source-drain contact is aligned with an outside edge of each individual outer spacer.Type: ApplicationFiled: February 24, 2014Publication date: August 27, 2015Applicant: International Business Machines CorporationInventors: Anirban Basu, Amlan Majumdar, Kuen-Ting Shiu, Yanning Sun
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Patent number: 9105571Abstract: Techniques for fabricating self-aligned contacts in III-V FET devices are provided. In one aspect, a method for fabricating a self-aligned contact to III-V materials includes the following steps. At least one metal is deposited on a surface of the III-V material. The at least one metal is reacted with an upper portion of the III-V material to form a metal-III-V alloy layer which is the self-aligned contact. An etch is used to remove any unreacted portions of the at least one metal. At least one impurity is implanted into the metal-III-V alloy layer. The at least one impurity implanted into the metal-III-V alloy layer is diffused to an interface between the metal-III-V alloy layer and the III-V material thereunder to reduce a contact resistance of the self-aligned contact.Type: GrantFiled: February 8, 2012Date of Patent: August 11, 2015Assignee: International Business Machines CorporationInventors: Christian Lavoie, Uzma Rana, Devendra K. Sadana, Kuen-Ting Shiu, Paul Michael Solomon, Yanning Sun, Zhen Zhang
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Patent number: 9093532Abstract: A semiconductor structure that includes a semiconductor fin comprising an III-V compound semiconductor material. A functional gate structure straddles a portion of the semiconductor fin. A semiconductor channel material having an electron mobility greater than silicon and comprising a different semiconductor material than the semiconductor fin and is located beneath the functional gate structure. The semiconductor channel material is present on at least each vertical sidewall of the semiconductor fin. A dielectric spacer is located on each vertical sidewall surface of the functional gate structure. A doped semiconductor is located on each side of the functional gate structure and underneath each dielectric spacer. A portion of the doped semiconductor material located beneath each dielectric spacer directly contacts a sidewall surface of semiconductor channel material located on each vertical sidewall of the semiconductor fin.Type: GrantFiled: June 21, 2013Date of Patent: July 28, 2015Assignee: International Business Machines CorporationInventors: Cheng-Wei Cheng, Effendi Leobandung, Kuen-Ting Shiu, Yanning Sun