Abstract: One aspect of the present disclosure pertains to a method of forming a semiconductor structure. The method includes forming an active region over a substrate, forming a dummy gate layer over the active region, forming a hard mask layer over the dummy gate layer, forming a patterned photoresist over the hard mask layer, and performing an etching process to the hard mask layer and the dummy gate layer using the patterned photoresist, thereby forming patterned hard mask structures and patterned dummy gate structures. The patterned hard mask structures are formed with an uneven profile having a protruding portion. The protruding portion of each of the patterned hard mask structures has a first width, wherein each of the patterned dummy gate structures has a second width, and the first width is greater than the second width.

Abstract: A refrigerant system including a compressor, an oil separator, an oil solenoid valve, a condenser, an evaporator, a bypass pipe, and a bypass solenoid valve is disclosed. The oil separator is connected to an output end of the compressor. The oil solenoid valve is disposed between the oil cooler and the compressor. The condenser is connected to the oil separator. The evaporator is connected to the condenser. The bypass pipe has a first end and a second end opposite to the first end. The first end is connected between the oil separator and the condenser, and the second end is connected between the evaporator and an input end of the compressor. The bypass solenoid valve is disposed on the bypass pipe. A controlling method for the refrigerant system is also disclosed.

Abstract: A two-stage refrigerant compressor and an operation method thereof are disclosed. The two-stage refrigerant compressor (10) includes: a housing (1); a first compressor module (2) having first screw rods (21) and a first motor (22) driving the first screw rods (21) to rotate; a second compressor module (3) having second screw rods (31) and a second motor (32) driving the second screw rods (31) to rotate; an adjustment mechanism (4) having a first slide valve (41) and a second slide valve (42); a middle pressure sensor (51) configured to acquire a current middle pressure; and a processor configured to receive data of the current middle pressure, control rotating speeds of the first motor (22) and the second motor (32), and control locations of the first slide valve (41) and the second slide valve (42).

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a gallium nitride (GaN) layer on a substrate; an aluminum gallium nitride (AlGaN) layer disposed on the GaN layer; a gate stack disposed on the AlGaN layer; a source feature and a drain feature disposed on the AlGaN layer and interposed by the gate stack; a dielectric material layer is disposed on the gate stack; and a field plate disposed on the dielectric material layer and electrically connected to the source feature, wherein the field plate includes a step-wise structure.

Abstract: A fluid machine and its operating method are provided. The fluid machine (10) includes a main body (1), a screw set (2), a capacity adjustment mechanism (3), an intermediate pressure sensor (5), and a controller (6). The main body (1) includes a low-pressure chamber (11), an intermediate-pressure chamber (12), and a high-pressure chamber (13). The screw set (2) includes a pair of first screws (21) in the low-pressure chamber (11) and a pair of second screws (22) in the high-pressure chamber (13). The capacity adjustment mechanism (4) includes a first slide valve (41) disposed corresponding to the first screws (21) and a second slide valve (42) disposed corresponding to the second screws (22). The intermediate pressure sensor (5) is placed in the intermediate-pressure chamber (12) for obtaining its interior pressure. The controller (6) drives movement of the first slide valve (41) and the second slide valve (42).

Abstract: A static random access memory (SRAM) cell includes a write port including a first inverter including a first pull-up transistor and a first pull-down transistor, and a second inverter including a second pull-up transistor and a second pull-down transistor and cross-coupled with the first inverter; and a read port including a read pass-gate transistor and a read pull-down transistor serially connected to each. A first doped concentration of impurities doped in channel regions of the second pull-down transistor and the read pull-down transistor is greater than a second doped concentration of the impurities doped in a channel region of the first pull-down transistor, or the impurities are doped in the channel regions of the second pull-down transistor and the read pull-down transistor and are not doped in the channel region of the first pull-down transistor.

Abstract: Various embodiments of the present disclosure are directed towards a two-dimensional carrier gas (2DCG) semiconductor device comprising an ohmic source/drain electrode with a plurality of protrusions separated by gaps and protruding from a bottom surface of the ohmic source/drain electrode. The ohmic source/drain electrode overlies a semiconductor film, and the protrusions extend from the bottom surface into the semiconductor film. Further, the ohmic source/drain electrode is separated from another ohmic source/drain electrode that also overlies the semiconductor film. The semiconductor film comprises a channel layer and a barrier layer that are vertically stacked and directly contact at a heterojunction. The channel layer accommodates a 2DCG that extends along the heterojunction and is ohmically coupled to the ohmic source/drain electrode and the other ohmic source/drain electrode. A gate electrode overlies the semiconductor film between the ohmic source/drain electrode and the other source/drain electrode.

Abstract: The present invention provides a photovoltaic panel packaging structure and method for the same. The packaging structure comprises a frame and a solar photovoltaic panel. The solar photovoltaic panel includes a first frame surface and a second frame surface with a receiving space and grooves formed therein. The a solar photovoltaic panel is installed in the receiving space and stacked on top of a first stop portion. The solar photovoltaic panel includes a first encapsulating layer, a second encapsulating layer. The first encapsulating layer includes a plurality of engaging strips extending along the edges of the solar photovoltaic panel, the engaging strips are respectively embedded in the corresponding grooves to hold the solar photovoltaic panel in place in the frame. Meanwhile, a third encapsulating layer extends to connect to the second frame surface. As a result, weight and thickness can be reduced while reducing multiple packaging passes and simplifying the assembly process.

Abstract: Various embodiments of the present disclosure are directed towards a two-dimensional carrier gas (2DCG) semiconductor device comprising an ohmic source/drain electrode with a plurality of protrusions separated by gaps and protruding from a bottom surface of the ohmic source/drain electrode. The ohmic source/drain electrode overlies a semiconductor film, and the protrusions extend from the bottom surface into the semiconductor film. Further, the ohmic source/drain electrode is separated from another ohmic source/drain electrode that also overlies the semiconductor film. The semiconductor film comprises a channel layer and a barrier layer that are vertically stacked and directly contact at a heterojunction. The channel layer accommodates a 2DCG that extends along the heterojunction and is ohmically coupled to the ohmic source/drain electrode and the other ohmic source/drain electrode. A gate electrode overlies the semiconductor film between the ohmic source/drain electrode and the other source/drain electrode.

Abstract: A semiconductor structure includes: a channel layer; an active layer over the channel layer, wherein the active layer is configured to form a two-dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer; a gate electrode over a top surface of the active layer; and a source/drain electrode over the top surface of the active layer; wherein the active layer includes a first layer and a second layer sequentially disposed therein from the top surface to a bottom surface of the active layer, and the first layer possesses a higher aluminum (Al) atom concentration compared to the second layer. An HEMT structure and an associated method are also disclosed.

Abstract: The present disclosure relates an integrated chip. The integrated chip includes an isolation region disposed within a substrate and surrounding an active area. A gate structure is disposed over the substrate and has a base region and a gate extension finger protruding outward from a sidewall of the base region along a first direction to past opposing sides of the active area. A source contact and a drain contact are disposed within the active area. The drain contact is separated from the source contact by the gate extension finger. A first plurality of conductive contacts are arranged on the gate structure. The first plurality of conductive contacts are separated along the first direction by distances overlying the gate extension finger.

Abstract: A knob on a touch panel includes a rotary wheel, a common pad, at least one sensing pad, a plurality of connectors and a conductive ring. The rotary wheel is mounted on the touch panel. The common pad is deployed on the touch panel. The at least one sensing pad is deployed on the touch panel. Each of the plurality of connectors is coupled between the rotary wheel and one pad among the at least one sensing pad and the common pad, to control each of the at least one sensing pad to be coupled to the common pad or not through the rotary wheel according to an operation of the knob. The conductive ring is deployed on a surface of the rotary wheel, to detect a touch object.

Abstract: A Static Random Access Memory (SRAM) cell includes a write port including a first inverter including a first pull-up transistor and a first pull-down transistor, and a second inverter including a second pull-up transistor and a second pull-down transistor and cross-coupled with the first inverter; and a read port including a read pass-gate transistor and a read pull-down transistor serially connected to each. A first doped concentration of impurities doped in channel regions of the second pull-down transistor and the read pull-down transistor is greater than a second doped concentration of the impurities doped in a channel region of the first pull-down transistor, or the impurities are doped in the channel regions of the second pull-down transistor and the read pull-down transistor and are not doped in the channel region of the first pull-down transistor.

Abstract: The present disclosure relates an integrated chip. The integrated chip includes an isolation region disposed within a substrate and surrounding an active area. A gate structure is disposed over the substrate and has a base region and a gate extension finger protruding outward from a sidewall of the base region along a first direction to past opposing sides of the active area. A source contact is disposed within the active area and a drain contact is disposed within the active area and is separated from the source contact by the gate extension finger. A first plurality of conductive contacts are arranged on the gate structure and separated along the first direction. The first plurality of conductive contacts are separated by distances overlying the gate extension finger.

Abstract: A question-answering learning method including the following steps is provided. Firstly, several classifiers are created according to N1 labeled sentences among N sentences. Then, at least one corresponding sentence type of each of the N2 unlabeled sentences among the N sentences is determined by each classifier. Then, N3 sentences are selected from the N2 unlabeled sentences according to a degree of consistency of determined results of the classifiers, wherein the determined results of the N3 sentences are determined by the classifiers and are inconsistent. Then, N4 mutually complementary sentences are selected as to-be-labeled sentences from the N3 sentences. Then, after the N4 selected to-be-labeled sentences are labeled, several classifiers are re-created according to the N1 labeled sentences and the N4 selected to-be-labeled sentences. Then, at least one of the previously created classifiers is added to the currently created classifiers to be members of the classifiers.

Abstract: A method for fabricating a memory device includes: providing a substrate; forming a first dielectric layer over the substrate; forming a plurality of conductive layers and a plurality of dielectric layers alternately and horizontally disposed on the substrate; forming a channel column structure on the substrate and in the plurality of conductive layers and the plurality of dielectric layers, where a side wall of the channel column structure is in contact with the plurality of conductive layers; forming a second dielectric layer covering the first dielectric layer; and forming, in the first and second dielectric layers, a conductive column structure adjacent to the channel column structure and in contact with one of the plurality of conductive layers, where the conductive column structure includes a liner insulating layer as a shell layer.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure, the method includes forming a buffer layer over a substrate. An active layer is formed on the buffer layer. A top electrode is formed on the active layer. An etch process is performed on the buffer layer and the substrate to define a plurality of pillar structures. The plurality of pillar structures include a first pillar structure laterally offset from a second pillar structure. At least portions of the first and second pillar structures are spaced laterally between sidewalls of the top electrode.

Abstract: A garden shears has an anvil portion, a driving arm, a blade portion and a plurality of pivot shafts. The anvil portion sandwiched an anvil, and the anvil portion and the driving arm are pivoted together by a pivot shaft. A gear and the blade portion are disposed between the driving arm. The blade portion has a straight groove and a rack portion. A pivot shaft is used to pivot the gear and the driving together is engaged and another pivot shaft passes through the straight groove and the driving arm with the pivot shaft capable of sliding in the straight groove and the gear being engaged with the rack portion to achieve the effect of a stable speed.

Abstract: A media item to be provided to users of a platform is identified. The media item is associated with a media class of one or more media classes. An indication of the media item is provided as input to a machine learning model trained based on historical encoding data to predict, for a given media item, a set of encoder parameter settings that satisfy a performance criterion in view of a respective media class of the given media item. The historical encoding data includes a prior set of encoder parameter settings that satisfied the performance criterion with respect to a prior media item associated with the respective class. Encoder parameter settings that satisfy the performance criterion in view of the media class is determined based on an output of the model. The media item is caused to be encoded using the determined encoder parameter settings.

Abstract: A garden shears has an anvil portion, a driving arm, a blade portion and a plurality of pivot shafts. The anvil portion sandwiched an anvil, and the anvil portion and the driving arm are pivoted together by a pivot shaft. A gear and the blade portion are disposed between the driving arm. The blade portion has a straight groove and a rack portion. A pivot shaft is used to pivot the gear and the driving together is engaged and another pivot shaft passes through the straight groove and the driving arm with the pivot shaft capable of sliding in the straight groove and the gear being engaged with the rack portion to achieve the effect of a stable speed.