Patents by Inventor Yao-Hung Liu

Yao-Hung Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200388759
    Abstract: The present invention relates to a structure of a memory device. The structure of a memory device includes a substrate, including a bottom electrode layer formed therein. A buffer layer is disposed on the substrate, in contact with the bottom electrode layer. A resistive layer surrounds a whole sidewall of the buffer layer, and extends upward vertically from the substrate. A mask layer is disposed on the buffer layer and the resistive layer. A noble metal layer is over the substrate, and fully covers the resistive layer and the mask layer. A top electrode layer is disposed on the noble metal layer.
    Type: Application
    Filed: July 8, 2019
    Publication date: December 10, 2020
    Applicant: United Microelectronics Corp.
    Inventors: HAI TAO LIU, Li Li Ding, Yao-Hung Liu, Guoan Du, Qi Lu Li, Chunlei Wan, Yi Yu Lin, Yuchao Chen, Huakai Li, Hung-Yueh Chen
  • Publication number: 20200083380
    Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.
    Type: Application
    Filed: October 8, 2018
    Publication date: March 12, 2020
    Inventors: Chien-Ming Lai, Yen-Chen Chen, Jen-Po Huang, Sheng-Yao Huang, Hui-Ling Chen, Qinggang Xing, Ding-Lung Chen, Li Li Ding, Yao-Hung Liu
  • Publication number: 20190267492
    Abstract: A semiconductor device includes an oxide semiconductor layer, disposed over a substrate. A source electrode of a metal nitride is disposed on the oxide semiconductor layer. A drain electrode of the metal nitride is disposed on the oxide semiconductor layer. A metal-nitride oxidation layer is formed on a surface of the source electrode and the drain electrode. A ratio of a thickness of the metal-nitride oxidation layer to a thickness of the drain electrode or the source electrode is equal to or less than 0.2.
    Type: Application
    Filed: May 15, 2019
    Publication date: August 29, 2019
    Applicant: United Microelectronics Corp.
    Inventors: Yen-Chen Chen, Xiao Wu, Hai Tao Liu, Ming Hua Du, Shouguo Zhang, Yao-Hung Liu, Chin-Fu Lin, Chun-Yuan Wu
  • Patent number: 10340391
    Abstract: A semiconductor device includes an oxide semiconductor layer, disposed over a substrate. A source electrode of a metal nitride is disposed on the oxide semiconductor layer. A drain electrode of the metal nitride is disposed on the oxide semiconductor layer. A metal-nitride oxidation layer is formed on a surface of the source electrode and the drain electrode. A ratio of a thickness of the metal-nitride oxidation layer to a thickness of the drain electrode or the source electrode is equal to or less than 0.2.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: July 2, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Yen-Chen Chen, Xiao Wu, Hai Tao Liu, Ming Hua Du, Shouguo Zhang, Yao-Hung Liu, Chin-Fu Lin, Chun-Yuan Wu
  • Publication number: 20190006519
    Abstract: A semiconductor device includes an oxide semiconductor layer, disposed over a substrate. A source electrode of a metal nitride is disposed on the oxide semiconductor layer. A drain electrode of the metal nitride is disposed on the oxide semiconductor layer. A metal-nitride oxidation layer is formed on a surface of the source electrode and the drain electrode. A ratio of a thickness of the metal-nitride oxidation layer to a thickness of the drain electrode or the source electrode is equal to or less than 0.2.
    Type: Application
    Filed: June 29, 2017
    Publication date: January 3, 2019
    Applicant: United Microelectronics Corp.
    Inventors: Yen-Chen Chen, Xiao Wu, Hai Tao Liu, Ming Hua Du, Shouguo Zhang, Yao-Hung Liu, Chin-Fu Lin, Chun-Yuan Wu
  • Publication number: 20110296634
    Abstract: A wafer side edge cleaning apparatus includes: a cleaning device including a fixing element and a wafer brush disposed beneath the fixing element. The wafer brush is in the shape of a frustum. The frustum has a tapered surface contacting with a side edge of a wafer. The top surface of the frustum is larger than the bottom surface of the frustum. When cleaning the side edge of the wafer, the wafer and the wafer brush are rotated in different directions and a cleaning solution flows out from the fixing element rinses and washes the side edge brush.
    Type: Application
    Filed: June 2, 2010
    Publication date: December 8, 2011
    Inventors: JINGDONG JIA, CHEE MONG LOO, MINGKUI Zhang, Yao-Hung Liu
  • Publication number: 20090056625
    Abstract: A shielding member applicable in a deposition apparatus is provided. The shielding member includes a base metal and an adhesion promoter layer arc-sprayed on the base metal, wherein adhesion promoter layer has a thickness gradient increasing from an upper end of the shielding member to a lower end of the shielding member. More preferably, no adhesion promoter layer is formed in the upper 10 cm of the shielding member, adjacent to a target layer.
    Type: Application
    Filed: August 29, 2007
    Publication date: March 5, 2009
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chee-Mong Loo, Yao-Hung Liu
  • Patent number: 6390902
    Abstract: The present invention provides a multi-conditioner arrangement of a CMP system. The CMP system according to the present invention comprises a polishing table, a polishing pad positioned on the polishing table, a plurality of carrier heads on the polishing pad functioning in holding semiconductor wafers, and a plurality of conditioners positioned between the two neighboring carrier heads on the polishing pad for recovering the surface texture of the polishing pad. Herein, a plurality of conditioners are in a one-to-one arrangement to a plurality of carrier heads, each conditioner producing a back and forth motion in a radiant direction. Therefore, the lifetime of the polishing pad is extended, the wafer-to-wafer difference is reduced, and spatial coverage is increased.
    Type: Grant
    Filed: June 6, 2001
    Date of Patent: May 21, 2002
    Assignee: United Microelectronics Corp.
    Inventors: Ruoh-Haw Chang, Hung-Yu Kuo, Yao-Hung Liu, De-Can Liao