Abstract: A memory film and a semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a metallic barrier material portion can be formed in each backside recess. A molybdenum-containing portion can be formed in each backside recess. Each backside recess can be filled with a molybdenum-containing portion alone, or can be filled with a combination of a molybdenum-containing portion and a metallic material portion including a material other than molybdenum.

Abstract: Contacts to peripheral devices extending through multiple tier structures of a three-dimensional memory device can be formed with minimal additional processing steps. First peripheral via cavities through a first tier structure can be formed concurrently with formation of first memory openings. Sacrificial via fill structures can be formed in the first peripheral via cavities concurrently with formation of sacrificial memory opening fill structures that are formed in the first memory openings. Second peripheral via cavities through a second tier structure can be formed concurrently with formation of word line contact via cavities that extend to top surfaces of electrically conductive layers in the first and second tier structures. After removal of the sacrificial via fill structures, the first and second peripheral via cavities can be filled with a conductive material to form peripheral contact via structures concurrently with formation of word line contact via structures.

Abstract: Methods of making a monolithic three dimensional NAND string that include forming a stack of alternating first material layers and second material layers over a substrate, where each of the second material layers includes a layer of a first silicon oxide material between two layers of a second silicon oxide material different from the first silicon oxide material, etching the stack to form a front side opening in the stack, forming a memory film over a sidewall of the front side opening, and forming a semiconductor channel in the front side opening such that at least a portion of the memory film is located between the semiconductor channel and the sidewall of the front side opening, where at least one of an air gap or a material which has a dielectric constant below 3.9 is formed between the respective two layers of second silicon oxide material.

Abstract: A monolithic three-dimensional memory device includes a first memory block containing a plurality of memory sub-blocks located on a substrate. Each memory sub-block includes a set of memory stack structures and a portion of alternating layers laterally surrounding the set of memory stack structures. The alternating layers include insulating layers and electrically conductive layers. A first portion of a neighboring pair of memory sub-blocks is laterally spaced from each other along a first horizontal direction by a backside contact via structure. A subset of the alternating layers contiguously extends between a second portion of the neighboring pair of memory sub-blocks through a gap in a bridge region between two portions of the backside contact via structure that are laterally spaced apart along a second horizontal direction to provide a connecting portion between the neighboring pair of memory sub-blocks.

Abstract: Systems and methods for implementing and using stacked vertical memory array architectures. A first NAND string may be formed or arranged above a second NAND string. The first NAND string may include a first drain-side select gate connected to a first set of memory cell transistors connected to a first source-side select gate. The second NAND string may include a second drain-side select gate connected to a second set of memory cell transistors connected to a second source-side select gate. The first NAND string and the second NAND string may comprise portions of the same or different memory array architectures (e.g., the first NAND string may be part of a memory array that uses U-shaped NAND strings and the second NAND string may be part of a memory array that uses single vertical NAND strings).

Abstract: Methods of making monolithic three-dimensional memory devices include performing a first etch to form a memory opening and a second etch using a different etching process to remove a damaged portion of the semiconductor substrate from the bottom of the memory opening. A single crystal semiconductor material is formed over the substrate in the memory opening using an epitaxial growth process. Additional embodiments include improving the quality of the interface between the semiconductor channel material and the underlying semiconductor layers in the memory opening which may be damaged by the bottom opening etch, including forming single crystal semiconductor channel material by epitaxial growth from the bottom surface of the memory opening and/or oxidizing surfaces exposed to the bottom opening etch and removing the oxidized surfaces prior to forming the channel material. Monolithic three-dimensional memory devices formed by the embodiment methods are also disclosed.

Abstract: A silicon-containing nucleation layer can be employed to provide a self-aligned template for selective deposition of tungsten within backside recesses during formation of a three-dimensional memory device. The silicon-containing nucleation layer may remain as a silicon layer, converted into a tungsten silicide layer, or replaced with a tungsten nucleation layer. Tungsten deposition can proceed only on the surface of the silicon-containing nucleation layer or a layer derived therefrom in a subsequent tungsten deposition process.

Abstract: A first stack of alternating layers including first electrically insulating layers and first sacrificial material layers is formed with first stepped surfaces. First memory openings can be formed in a device region outside of the first stepped surfaces, and first support openings can be formed through the first stepped surfaces. The first memory openings and the first support openings can be filled with a sacrificial fill material. A second stack of alternating layers including second electrically insulating layers and second sacrificial material layers can be formed over the first stack. Inter-stack memory openings including the first memory openings can be formed in the device region, and inter-stack support openings including the first support openings can be formed in a steppes surface region. Memory stack structures and support pillar structure are simultaneously formed in the inter-stack memory openings and the inter-stack support openings, respectively.

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed on a substrate. Separator insulator structures can be optionally formed through the alternating stack. Memory opening are formed through the alternating stack, and the sacrificial material layers are removed selective to the insulating layers. Electrically conductive layers are formed in the lateral recesses by deposition of at least one conductive material. Metal-semiconductor alloy regions are appended to the electrically conductive layers by depositing at least a semiconductor material and inducing reaction of the semiconductor material with the material of the electrically conductive layers and/or a sacrificial metal layer. Memory stack structures can be formed in the memory openings and directly on the metal-semiconductor alloy regions of the electrically conductive layers.

Abstract: A monolithic three-dimensional memory device includes a first memory block containing a plurality of memory sub-blocks located on a substrate. Each memory sub-block includes a set of memory stack structures and a portion of alternating layers laterally surrounding the set of memory stack structures. The alternating layers include insulating layers and electrically conductive layers. A first portion of a neighboring pair of memory sub-blocks is laterally spaced from each other along a first horizontal direction by a backside contact via structure. A subset of the alternating layers contiguously extends between a second portion of the neighboring pair of memory sub-blocks through a gap in a bridge region between two portions of the backside contact via structure that are laterally spaced apart along a second horizontal direction to provide a connecting portion between the neighboring pair of memory sub-blocks.

Abstract: A three-dimensional memory device including multiple stack structures can be formed with a joint region electrode, which is an electrode formed at a joint region located near the interface between an upper stack structure and a lower stack structure. A memory stack structure is formed through the multiple stack structures. The joint region electrode laterally surrounds a portion of the memory stack structure in proximity to the interface between different stack structures. The joint region electrode includes a layer portion having a thickness and a collar portion that laterally surrounds the memory stack structure and having a greater vertical extent than the thickness of the layer portion. The increased vertical extent of the collar portion with respect to the vertical extent of the layer portion provides enhanced control of a portion of a semiconductor channel in the memory stack structure located near the interface between different stack structures.

Abstract: A method of making a semiconductor device includes forming a stack of alternating layers of a first material and a second material over a substrate, etching the stack to form at least one opening in the stack such that a damaged region is located on a bottom surface of the at least one opening, forming a masking layer on a sidewall of the at least one opening while the bottom surface of the at least one opening is not covered by the masking layer, and further etching the bottom surface of the at least one opening remove the damaged region.

Abstract: A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of insulating first material and sacrificial second material different from the first material over a major surface of the substrate, forming a front side opening in the stack, forming at least one charge storage region in the front side opening and forming a tunnel dielectric layer over the at least one charge storage region in front side opening. The method also includes forming a semiconductor channel over the tunnel dielectric layer in the front side opening, forming a back side opening in the stack and selectively removing at least portions of the second material layers to form back side recesses between adjacent first material layers.

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed on a substrate. Separator insulator structures can be optionally formed through the alternating stack. Memory opening are formed through the alternating stack, and the sacrificial material layers are removed selective to the insulating layers. Electrically conductive layers are formed in the lateral recesses by deposition of at least one conductive material. Metal-semiconductor alloy regions are appended to the electrically conductive layers by depositing at least a semiconductor material and inducing reaction of the semiconductor material with the material of the electrically conductive layers and/or a sacrificial metal layer. Memory stack structures can be formed in the memory openings and directly on the metal-semiconductor alloy regions of the electrically conductive layers.

Abstract: A monolithic three dimensional NAND string includes a semiconductor channel, where at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate, an interlevel insulating layer located between adjacent control gate electrodes, a blocking dielectric layer located in contact with the plurality of control gate electrodes and an interlevel insulating layer, a charge storage layer located at least partially in contact with the blocking dielectric layer, and a tunnel dielectric located between the charge storage layer and the semiconductor channel. The charge storage layer has a curved profile.

Abstract: A three-dimensional memory device including multiple stack structures can be formed with a joint region electrode, which is an electrode formed at a joint region located near the interface between an upper stack structure and a lower stack structure. A memory stack structure is formed through the multiple stack structures. The joint region electrode laterally surrounds a portion of the memory stack structure in proximity to the interface between different stack structures. The joint region electrode includes a layer portion having a thickness and a collar portion that laterally surrounds the memory stack structure and having a greater vertical extent than the thickness of the layer portion. The increased vertical extent of the collar portion with respect to the vertical extent of the layer portion provides enhanced control of a portion of a semiconductor channel in the memory stack structure located near the interface between different stack structures.

Abstract: A monolithic three dimensional NAND string including a stack of alternating first material layers and second material layers different from the first material layers over a major surface of a substrate. The first material layers include a plurality of control gate electrodes and the second material layers include an insulating material and the plurality of control gate electrodes extend in a first direction. The NAND string also includes a semiconductor channel, a blocking dielectric, and a plurality of vertically spaced apart floating gates. Each of the plurality of vertically spaced apart floating gates or each of the second material layers includes a first portion having a first thickness in the second direction, and a second portion adjacent to the first portion in the first direction and having a second thickness in the second direction which is different than the first thickness.

Abstract: A method of making a vertical NAND device includes forming a lower portion of a memory stack over a substrate, forming a lower portion of memory openings in the lower portion of the memory stack, and at least partially filling the lower portion of the memory openings with a sacrificial material. The method also includes forming an upper portion of the memory stack over the lower portion of the memory stack and over the sacrificial material, forming an upper portion of the memory openings in the upper portion of the memory stack to expose the sacrificial material in the lower portion of the memory openings, removing the sacrificial material to connect the lower portion of the memory openings with a respective upper portion of the memory openings to form continuous memory openings, and forming a semiconductor channel in each continuous memory opening.

Abstract: Blocking dielectric structures and/or thicker barrier metal films for preventing or reducing fluorine diffusion are provided. A blocking dielectric layer can be formed as an outer layer of a memory film in a memory stack structure extending through electrically insulating layers and sacrificial material layers. After formation of backside recesses by removal of the sacrificial material layers, dopants can be introduced into physically exposed portions of the blocking dielectric layer, for example, by plasma treatment or thermal treatment, to form silicon oxynitride regions which can reduce or prevent fluorine diffusion. Alternatively or additionally, a set of metal oxide blocking dielectric material portions can be formed in the backside recesses to retard or prevent fluorine diffusion. To minimize adverse impact on the electrically conductive layers formed in the backside recesses, the blocking dielectric material portions can be laterally recessed from a trench employed to form the backside recesses.

Abstract: A memory device includes a stack of material layers with a plurality of NAND strings extending through the stack, and a trench through the stack with a pair of sidewalls defining a width of the trench that is substantially constant or decreases from the top of the trench to a first depth and increases between a first depth and a second depth that is closer to the bottom of the trench than the first depth and the trench has an insulating material covering at least the trench sidewalls. Further embodiments include a memory device including a stack of material layers and an active memory cell region defined between a pair of trenches, and within the active region the stack comprises alternating layers of a first material and a second material, and outside of the active region the stack comprises alternating layers of the first material and a third material.