Abstract: The present disclosure, in some embodiments, relates to a memory device. The memory device includes a bottom electrode disposed over a lower interconnect within a lower inter-level dielectric (ILD) layer over a substrate. A data storage structure is over the bottom electrode. A first top electrode layer is disposed over the data storage structure, and a second top electrode layer is on the first top electrode layer. The second top electrode layer is less susceptible to oxidation than the first top electrode layer. A top electrode via is over and electrically coupled to the second top electrode layer.

Abstract: A semiconductor structure is provided. The semiconductor structure includes metallization structure, a plurality of conductive pads, and a dielectric layer. The plurality of conductive pads is over the metallization structure. The dielectric layer is on the metallization structure and covers the conductive pad. The dielectric layer includes a first dielectric film, a second dielectric film, and a third dielectric film. The first dielectric film is on the conductive pad. The second dielectric film is on the first dielectric film. The third dielectric film is on the second dielectric film. The a refractive index of the first dielectric film is smaller than a refractive index of the second dielectric film, and the refractive index of the second dielectric film is smaller than a refractive index of the third dielectric film.

Abstract: A structure includes a semiconductor substrate, a conductor-insulator-conductor capacitor. The conductor-insulator-conductor capacitor is disposed on the semiconductor substrate and includes a first conductor, a nitrogenous dielectric layer and a second conductor. The nitrogenous dielectric layer is disposed on the first conductor and the second conductor is disposed on the nitrogenous dielectric layer.

Abstract: Various embodiments of the present disclosure are directed towards a display device. The display device includes an isolation structure disposed over a semiconductor substrate. An electrode is disposed at least partially over the isolation structure. A light-emitting structure is disposed over the electrode. A conductive reflector is disposed below the isolation structure and electrically coupled to the electrode. The conductive reflector is disposed at least partially between sidewalls of the light-emitting structure. The conductive reflector comprises a non-metal-doped aluminum material.

Abstract: A memory device includes a conductive strip stack structure having conductive strips and insulating layers stacked in a staggered manner and a channel opening passing through the conductive strips and the insulating layer; a memory layer disposed in the channel opening and overlying the conductive strips; a channel layer overlying the memory layer; a semiconductor pad extending upwards from a bottom of the channel opening beyond an upper surface of a bottom conductive strip, in contact with the channel layer, and electrically isolated from the conductive strips; wherein the channel layer includes a first portion having a first doping concentration and a second portion having a second doping concentration disposed on the first portion.

Abstract: Various embodiments of the present disclosure are directed towards a display device. The display device includes an isolation structure disposed over a semiconductor substrate. An electrode is disposed at least partially over the isolation structure. A light-emitting structure is disposed over the electrode. A conductive reflector is disposed below the isolation structure and electrically coupled to the electrode. The conductive reflector is disposed at least partially between sidewalls of the light-emitting structure. The conductive reflector comprises a non-metal-doped aluminum material.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a magnetoresistive random access memory (MRAM) cell over a substrate. A dielectric structure overlies the substrate. The MRAM cell is disposed within the dielectric structure. The MRAM cell includes a magnetic tunnel junction (MTJ) sandwiched between a bottom electrode and a top electrode. A conductive wire overlies the top electrode. A sidewall spacer structure continuously extends along a sidewall of the MTJ and the top electrode. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer sandwiched between the first and second sidewall spacer layers. The first and second sidewall spacer layers comprise a first material and the protective sidewall spacer layer comprises a second material different than the first material.

Abstract: A film stack and manufacturing method thereof are provided. The film stack includes a plurality of first metal-containing films, and a plurality of second metal-containing films. The first metal-containing films and the second metal-containing films are alternately stacked to each other. The first metal-containing films and the second metal-containing films comprise the same metal element and the same nonmetal element, and a concentration of the metal element in the second metal-containing film is greater than a concentration of the nonmetal element in the second metal-containing film.

Abstract: A memory device includes a semiconductor substrate, a stack, a charge storage structure, a blocking layer, a tunneling layer, and a channel layer. The stack is disposed on a principle surface of the semiconductor substrate and includes alternately arranged conductive layers and insulating layers. The charge storage structure includes bent storage structures or discrete storage segments. Each bent storage structure or each discrete storage segment is substantially aligned with a corresponding one of the conductive layers in a direction parallel to the principle surface. The blocking layer is at least partially interposed between the conductive layers and the bent storage structures or between the conductive layers and the discrete storage segments. The tunneling layer is disposed on the bent storage structures or the discrete storage segments. The channel layer is disposed on the tunneling layer.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a plurality of bond pad structures over an interconnect structure on a front-side of a semiconductor body. The plurality of bond pad structures respectively have a titanium contact layer. The interconnect structure and the semiconductor body are patterned to define trenches extending into the semiconductor body. A dielectric fill material is formed within the trenches. The dielectric fill material is etched to expose the titanium contact layer prior to bonding the semiconductor body to a carrier substrate. The semiconductor body is thinned to expose the dielectric fill material along a back-side of the semiconductor body and to form a plurality of integrated chip die. The dielectric fill material is removed to separate the plurality of integrated chip die.

Abstract: A memory device includes a conductive strip stack structure having conductive strips and insulating layers stacked in a staggered manner and a channel opening passing through the conductive strips and the insulating layer; a memory layer disposed in the channel opening and overlying the conductive strips; a channel layer overlying the memory layer; a semiconductor pad extending upwards from a bottom of the channel opening beyond an upper surface of a bottom conductive strip, in contact with the channel layer, and electrically isolated from the conductive strips; wherein the channel layer includes a first portion having a first doping concentration and a second portion having a second doping concentration disposed on the first portion.

Abstract: A method of forming a memory device is provided. In some embodiments, a memory cell is formed over a substrate, and a sidewall spacer layer is formed along the memory cell. A lower etch stop layer is formed on the sidewall spacer layer, and an upper dielectric layer is formed on the lower etch stop layer. A first etching process is performed to etch back the upper dielectric layer using the lower etch stop layer as an etch endpoint.

Abstract: The present disclosure provides a method for forming a semiconductor structure. The method includes the following operations. A metal layer is formed. An adhesion-enhancing layer is formed over the metal layer by a silicide operation. A dielectric stack is formed over the adhesion-enhancing layer. A trench is formed in the dielectric stack by removing a portion of dielectric stack aligning with the metal layer. A barrier layer is formed conforming to the sidewall of the trench. A high-k dielectric layer is formed conforming to the barrier layer. A contact is formed in the trench and be connected to the metal layer.

Abstract: A semiconductor structure includes a first source/drain region, a second source/drain region, a channel doping region, a gate structure, a first well and a second well. The second source/drain region is disposed opposite to the first source/drain region. The channel doping region is disposed between the first source/drain region and the second source/drain region. The gate structure is disposed on the channel doping region. The first well has a first portion disposed under the first source/drain region. The second well is disposed opposite to the first well and separated from the second source/drain region. The first source/drain region, the second source/drain region and the channel doping region have a first conductive type. The first well and the second well have a second conductive type different from the first conductive type.

Abstract: A method for forming a semiconductor structure includes following operations. A first substrate including a first side, a second side opposite to the first side, and a metallic pad disposed over the first side is received. A dielectric structure including a first trench directly above the metallic pad is formed. A second trench is formed in the dielectric structure and a portion of the first substrate. A sacrificial layer is formed to fill the first trench and the second trench. A third trench is formed directly above the metallic pad. A barrier ring and a bonding structure are formed in the third trench. A bonding layer is disposed to bond the first substrate to a second substrate. A portion of the second side of the first substrate is removed to expose the sacrificial layer. The sacrificial layer is removed by an etchant.

Abstract: A semiconductor device includes a substrate including a doped region of a first doping concentration that extends downward from an upper surface of the substrate; a first stack on the upper surface, including first insulating layers and first conductive layers alternatively stacked, a first channel layer, a first memory layer and a first conductive connector configured to receive a first voltage, the first conductive connector on the first channel layer, having a second doping concentration; a second stack on the first stack including second insulating layers and second conductive layers alternatively stacked, a second channel layer, a second memory layer, the second conductive layer configured to receive the second voltage; a second conductive connector on the second channel layer, configured to receive an erasing voltage, the first conductive connector electrically connected to the first and second channel layers; the first doping concentration smaller than the second doping concentration.

Abstract: An operating method of a non-volatile memory includes: generating a first programming pulse with a first time period to a target memory cell in a memory array; reading and verifying whether a threshold voltage of the target memory cell reaches a target voltage level; and generating a second programming pulse with a second time period to the target memory cell when the threshold voltage of the target memory cell does not reach the target voltage level, wherein the second time period is longer than the first time period.

Abstract: A memory cell with an etch stop layer is provided. The memory cell comprises a bottom electrode disposed over a substrate. A switching dielectric is disposed over the bottom electrode and having a variable resistance. A top electrode is disposed over the switching dielectric. A sidewall spacer layer extends along sidewalls of the bottom electrode, the switching dielectric, and the top electrode and an upper surface of a lower dielectric layer. A lower etch stop layer is disposed over the lower dielectric layer and lining an outer sidewall of the sidewall spacer layer. The the sidewall spacer layer separates the lower etch stop layer from the lower dielectric layer.

Abstract: A semiconductor structure includes a first substrate, a metallic pad disposed over the first substrate, a dielectric structure disposed over the first substrate and exposing a portion of the metallic pad, a bonding structure disposed over and electrically connected to the metallic pad, a barrier ring surrounding the bonding structure, and a through-hole penetrating the first substrate and the dielectric structure. The bonding structure includes a bottom and a sidewall, the bottom of the bonding structure is in contact with the metallic pad, a first portion of the sidewall of the bonding structure is in contact with the dielectric structure, and a second portion of the sidewall of the bonding structure is in contact with the barrier ring.

Abstract: The present disclosure provides a semiconductor structure, including providing a metal layer, an adhesion-enhancing layer over the metal layer, a dielectric stack over the adhesion-enhancing layer, a contact penetrating the dielectric stack and the adhesion-enhancing layer and connecting with the metal layer, a barrier layer disposed between the contact and the dielectric stack, and a high-k dielectric layer disposed between the contact and the barrier layer.