Patents by Inventor Yark Yeon Kim
Yark Yeon Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090250756Abstract: An n-type SBTT and a manufacturing method thereof are provided. The SBTT includes a silicon layer, a gate, a double layer that has a rare-earth metal silicide layer and a transition metal silicide layer. The silicon layer has a channel region. The gate is formed in an overlapping manner on the channel region and has a gate dielectric layer on its interface with respect to the silicon layer. The double layer is formed as a source/drain that has the channel region interposed on the silicon layer.Type: ApplicationFiled: June 16, 2009Publication date: October 8, 2009Inventors: Yark Yeon Kim, Moon Gyu Jang, Jae Heon Shin, Seong Jae Lee
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Publication number: 20090215232Abstract: Provided are a Schottky barrier tunnel transistor and a method of manufacturing the same that are capable of minimizing leakage current caused by damage to a gate sidewall of the Schottky barrier tunnel transistor using a Schottky tunnel barrier naturally formed at a semiconductor-metal junction as a tunnel barrier. The method includes the steps of: forming a semiconductor channel layer on an insulating substrate; forming a dummy gate on the semiconductor channel layer; forming a source and a drain at both sides of the dummy gate on the insulating substrate; removing the dummy gate; forming an insulating layer on a sidewall from which the dummy gate is removed; and forming an actual gate in a space from which the dummy gate is removed. In manufacturing the Schottky barrier tunnel transistor using the dummy gate, it is possible to form a high-k dielectric gate insulating layer and a metal gate, and stable characteristics in silicidation of the metal layer having very strong reactivity can be obtained.Type: ApplicationFiled: May 4, 2009Publication date: August 27, 2009Inventors: Yark Yeon KIM, Seong Jae LEE, Moon Gyu JANG, Chel Jong CHOI, Myung Sim JUN, Byoung Chul PARK
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Patent number: 7566642Abstract: An n-type SBTT and a manufacturing method thereof are provided. The SBTT includes a silicon layer, a gate, a double layer that has a rare-earth metal silicide layer and a transition metal silicide layer. The silicon layer has a channel region. The gate is formed in an overlapping manner on the channel region and has a gate dielectric layer on its interface with respect to the silicon layer. The double layer is formed as a source/drain that has the channel region interposed on the silicon layer.Type: GrantFiled: July 22, 2005Date of Patent: July 28, 2009Assignee: Electronics and Telecommunications Research InstituteInventors: Yark Yeon Kim, Moon Gyu Jang, Jae Heon Shin, Seong Jae Lee
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Patent number: 7545000Abstract: Provided are a Schottky barrier tunnel transistor and a method of manufacturing the same that are capable of minimizing leakage current caused by damage to a gate sidewall of the Schottky barrier tunnel transistor using a Schottky tunnel barrier naturally formed at a semiconductor-metal junction as a tunnel barrier. The method includes the steps of: forming a semiconductor channel layer on an insulating substrate; forming a dummy gate on the semiconductor channel layer; forming a source and a drain at both sides of the dummy gate on the insulating substrate; removing the dummy gate; forming an insulating layer on a sidewall from which the dummy gate is removed; and forming an actual gate in a space from which the dummy gate is removed. In manufacturing the Schottky barrier tunnel transistor using the dummy gate, it is possible to form a high-k dielectric gate insulating layer and a metal gate, and stable characteristics in silicidation of the metal layer having very strong reactivity can be obtained.Type: GrantFiled: July 13, 2006Date of Patent: June 9, 2009Assignee: Electronics and Telecommunications Research InstituteInventors: Yark Yeon Kim, Seong Jae Lee, Moon Gyu Jang, Chel Jong Choi, Myung Sim Jun, Byoung Chul Park
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Publication number: 20080299736Abstract: Provided is a method of manufacturing a semiconductor device including a high-k dielectric thin layer formed using an interfacial reaction. The method includes the steps of: forming an oxide layer on a silicon substrate; depositing a metal layer on the oxide layer to form a metal silicate layer using an interfacial reaction between the oxide layer and the metal layer; forming a metal gate by etching the metal silicate layer and the metal layer; and forming a lightly doped drain (LDD) region and source and drain regions in the silicon substrate after forming the metal gate. In this method, a semiconductor device having high quality and performance can be manufactured by a simpler process at lower cost.Type: ApplicationFiled: March 11, 2008Publication date: December 4, 2008Applicant: Electronics and Telecommunications research InstituteInventors: Chel Jong Choi, Moon Gyu Jang, Yark Yeon Kim, Myung Sim Jun, Tae Youb Kim
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Publication number: 20080128760Abstract: Provided is a Schottky barrier nanowire field effect transistor, which has source/drain electrodes formed of metal silicide and a channel formed of a nanowire, and a method for fabricating the same. The Schottky barrier nanowire field effect transistor includes: a channel suspended over a substrate and including a nanowire; metal silicide source/drain electrodes electrically connected to both ends of the channel over the substrate; a gate electrode disposed to surround the channel; and a gate insulation layer disposed between the channel and the gate electrode.Type: ApplicationFiled: November 30, 2007Publication date: June 5, 2008Applicant: Electronics and Telecommunications Research InstituteInventors: Myungsim Jun, Moon-Gyu Jang, Yark-Yeon Kim, Chel-Jong Choi, Taeyoub Kim, Seongjae Lee
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Publication number: 20080128786Abstract: Provided are a high density semiconductor memory device capable of precisely reading data by suppressing the occurrence of a leakage current due to the high-integration of the semiconductor memory device, and a method for manufacturing the semiconductor memory device. The high density semiconductor memory device includes: source and drain electrodes disposed over a substrate, and forming a Schottky junction with a channel region; and a floating gate disposed over the substrate of the channel region, and configured with a plurality of nanodots. The nanodots may be formed of a silicon compound or any material that can be charged.Type: ApplicationFiled: December 4, 2007Publication date: June 5, 2008Applicant: Electronics and Telecommunications Research InstituteInventors: Taeyoub KIM, Myungsim JUN, Yark-Yeon KIM, Moon-Gyu JANG, Chel-Jong CHOI, Seong-Jae LEE, Byoungchul PARK
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Publication number: 20080132049Abstract: Provided is a method for fabricating a Schottky barrier tunnel transistor (SBTT) that can fundamentally prevent the generation of a gate leakage current caused by damage of spacers formed on both sidewalls of a gate electrode. The method for fabricating a Schottky barrier tunnel transistor, which includes: a) forming a silicon pattern and a sacrificial pattern on a buried oxide layer supported by a support substrate; b) forming a source/drain region on the buried oxide layer exposed on both sides of the silicon pattern, the source/drain region being formed of a metal layer and being in contact with both sidewalls of the silicon pattern; c) removing the sacrificial pattern to expose the top surface of the silicon pattern; and d) forming a gate insulating layer and a gate electrode on the exposed silicon pattern.Type: ApplicationFiled: October 31, 2007Publication date: June 5, 2008Applicant: Electronics and Telecommunications Research InstituteInventors: Yark-Yeon KIM, Seong-Jae Lee, Moon-Gyu Jang, Tae-Youb Kim, Chel-Jong Choi, Myung-Sim Jun, Byoung-Chul Park
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Publication number: 20080121868Abstract: A Schottky barrier tunnel transistor includes a gate electrode, and source and drain regions. The gate electrode is formed over a channel region of a substrate to form a Schottky junction with the substrate. The source and drain regions are formed in the substrate exposed on both sides of the gate electrode.Type: ApplicationFiled: May 8, 2007Publication date: May 29, 2008Inventors: Moon-Gyu Jang, Yark-Yeon Kim, Chel-Jong Choi, Myung-Sim Jun, Tae-Youb Kim, Seong-Jae Lee
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Publication number: 20080124854Abstract: A method for fabricating a semiconductor device includes forming a gate insulation layer over a substrate, forming a conductive compound containing layer over the gate insulation layer, etching the conductive compound containing layer and the gate insulation layer to form a gate structure, forming a metal layer over the resultant structure obtained after the etching, and letting the metal layer to react with silicon from the substrate to form source and drain regions comprising a metal silicide layer over the substrate exposed on both sides of the gate structure, wherein the conductive compound containing layer does not react with the metal layer.Type: ApplicationFiled: May 7, 2007Publication date: May 29, 2008Inventors: Chel-Jong CHOI, Moon-Gyu JANG, Yark-Yeon KIM, Tae-Youb KIM, Myung-Sim JUN, Seong-Jae LEE
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Patent number: 7312510Abstract: A device using an ambipolar transport of an SB-MOSFET and a method for operating the same are provided. The SB-MOSFET includes: a silicon channel region; a source and a drain contacted on both sides of the channel region and formed of material including metal layer; and a gate formed on the channel region, with a gate dielectric layer interposed therebetween. Positive (+), 0 or negative (?) gate voltage is selectively applied to the gate, the channel becomes off-state when the gate voltage between a negative threshold voltage and a positive threshold voltage is applied, and the channel becomes a first on-state and a second on-state when the gate voltage is lower than the negative threshold voltage or higher than the positive threshold voltage. Accordingly, it is possible to implement three current states, that is, hole current, electron current, and no current. The SB-MOSFET can be applied to a multi-bit memory and/or multi-bit logic device.Type: GrantFiled: July 22, 2005Date of Patent: December 25, 2007Assignee: Electronics and Telecommunications Research InstituteInventors: Jae Heon Shin, Moon Gyu Jang, Yark Yeon Kim, Seong Jae Lee
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Patent number: 7268407Abstract: Provided are a Schottky barrier tunnel single electron transistor and a method of manufacturing the same that use a Schottky barrier formed between metal and semiconductor by replacing a source and a drain with silicide as a reactant of silicon and metal, instead of a conventional method of manufacturing a single electron transistor (SET) that includes source and drain regions by implanting dopants such that an artificial quantum dot is formed in a channel region. As a result, it does not require a conventional PADOX process to form a quantum dot for a single electron transistor (SET), height and width of a tunneling barrier can be artificially adjusted by using silicide materials that have various Schottky junction barriers, and it is possible to improve current driving capability of the single electron transistor (SET).Type: GrantFiled: August 3, 2005Date of Patent: September 11, 2007Assignee: Electronics and Telecommunications Research InstituteInventors: Moon Gyu Jang, Yark Yeon Kim, Jae Heon Shin, Seong Jae Lee
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Patent number: 6693705Abstract: The present invention relates to an apparatus for measuring a slant angle in a solid immersion lens. In a near-field optical data storage head for storing/reading data using a solid immersion lens (SIL), a parallel light is formed within the plane of the solid immersion lens and the slant angle of the parallel light is then measured using the angle measurement principle of the autocollimator in order to measure the slant angle of the solid immersion lens. For this, the present invention includes an optical system for generating the parallel light within the solid immersion lens, and a unit for measuring the slant angle of the solid immersion lens using a location detection unit. An incident light becomes the parallel light by the optical system and the curved face of the solid immersion lens. The reflected light is also focused on the location detection unit. The location detection unit converts the reflection angle of the reflecting light into a location value to calculate the angle value.Type: GrantFiled: June 4, 2002Date of Patent: February 17, 2004Assignee: Electronics and Telecommunications Research InstituteInventors: Yeung Joon Sohn, Gee Pyeong Han, Yark Yeon Kim, Tae Youb Kim, Mun Cheol Paek, Kyoung Ik Cho
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Publication number: 20030123053Abstract: The present invention relates to an apparatus for measuring a slant angle in a solid immersion lens. In a near-field optical data storage head for storing/reading data using a solid immersion lens (SIL), a parallel light is formed within the plane of the solid immersion lens and the slant angle of the parallel light is then measured using the angle measurement principle of the autocollimator in order to measure the slant angle of the solid immersion lens. For this, the present invention includes an optical system for generating the parallel light within the solid immersion lens, and a unit for measuring the slant angle of the solid immersion lens using a location detection unit. An incident light becomes the parallel light by the optical system and the curved face of the solid immersion lens. The reflected light is also focused on the location detection unit. The location detection unit converts the reflection angle of the reflecting light into a location value to calculate the angle value.Type: ApplicationFiled: June 4, 2002Publication date: July 3, 2003Inventors: Yeung Joon Sohn, Gee Pyeong Han, Yark Yeon Kim, Tae Youb Kim, Mun Cheol Paek, Kyoung Ik Cho
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Patent number: 6147021Abstract: A dielectric ceramic composition for a microwave device including MgTiO.sub.3 and CaTiO.sub.3 as a main component and a Li.sub.2 CO.sub.3 as a sub-component is provided. The composition being expressed as follows: (94MgTiO.sub.3 -6CaTiO.sub.3)+xLi.sub.2 CO.sub.3 (mol %), where 0.2.ltoreq.x.ltoreq.0.8 (mol %). Therefore, it is capable of increasing a quality factor and decreasing a sintering temperature by adding a new component and effectively reproducing the above-described dielectric characteristic.Type: GrantFiled: November 6, 1998Date of Patent: November 14, 2000Assignees: Electronics and Telecommunications Research Institute, Korea TelecomInventors: Jin Woo Hahn, Duk Jun Kim, Gee Pyeong Han, Yark Yeon Kim, Sang Seok Lee, Tae Goo Choy
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Patent number: 6077802Abstract: A microwave dielectric ceramic composition is fabricated by adding one selected from a material containing Ba and a material containing Sr or a mixture of a material containing Ba and a material containing Sr to a composition formed of 25.about.43 wt % of TiO.sub.2, 39-57 wt % of ZrO.sub.2, and 7-28 wt % of SnO.sub.2 as an additive, wherein the additive is added by 0.2.about.8.0 wt % based on the total amount of the composition, and is capable of implementing a high dielectric constant and quality factor by sintering at a temperature of 1250.about.1400.degree. C.Type: GrantFiled: November 6, 1998Date of Patent: June 20, 2000Assignees: Electronics and Telecommunications Research Institute, Korea TelecomInventors: Jin Woo Hahn, Duk Jun Kim, Gee Pyeong Han, Yark Yeon Kim, Sang Seok Lee, Tae Goo Choy