Patents by Inventor Yasuaki Higuchi

Yasuaki Higuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10995422
    Abstract: A GaAs substrate has a first surface. The sum of the number of particles having a longer diameter of more than or equal to 0.16 ?m which are present in the first surface, per cm2 of the first surface, and the number of damages having a longer diameter of more than or equal to 0.16 ?m which are present in a second surface, per cm2 of the second surface, is less than or equal to 2.1, the second surface being formed by etching the first surface by 0.5 ?m in a depth direction.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: May 4, 2021
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shinya Fujiwara, Yasuaki Higuchi
  • Patent number: 10663277
    Abstract: An indium phosphide substrate, a method of inspecting thereof and a method of producing thereof are provided, by which an epitaxial film grown on the substrate is rendered excellently uniform, thereby allowing improvement in PL characteristics and electrical characteristics of an epitaxial wafer formed using this epitaxial film. The indium phosphide substrate has a first main surface and a second main surface, a surface roughness Ra1 at a center position on the first main surface, and surface roughnesses Ra2, Ra3, Ra4, and Ra5 at four positions arranged equidistantly along an outer edge of the first main surface and located at a distance of 5 mm inwardly from the outer edge. An average value m1 of the surface roughnesses Ra1, Ra2, Ra3, Ra4, and Ra5 is 0.5 nm or less, and a standard deviation ?1 of the surface roughnesses Ra1, Ra2, Ra3, Ra4, and Ra5 is 0.2 nm or less.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: May 26, 2020
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Shinya Fujiwara, Yasuaki Higuchi
  • Publication number: 20200131668
    Abstract: A gallium arsenide crystal substrate has a diameter not smaller than 150 mm and not greater than 205 mm and a thickness not smaller than 300 ?m and not greater than 800 ?m and includes any of a flat portion and a notch portion. In any of a first flat region and a first notch region, when an atomic concentration of silicon is not lower than 3.0×1016 cm?3 and not higher than 3.0×1019 cm?3, the gallium arsenide crystal substrate has an average dislocation density not lower than 0 cm?2 and not higher than 15000 cm?2, and when an atomic concentration of carbon is not lower than 1.0×1015 cm?3 and not higher than 5.0×1017 cm?3, the gallium arsenide crystal substrate has an average dislocation density not lower than 3000 cm?2 and not higher than 20000 cm?2.
    Type: Application
    Filed: February 23, 2018
    Publication date: April 30, 2020
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Masanori MORISHITA, Hidetoshi TAKAYAMA, Yasuaki HIGUCHI, Yoshiaki HAGI
  • Publication number: 20200066850
    Abstract: An indium phosphide crystal substrate has a diameter of 100-205 mm and a thickness of 300-800 ?m and includes any of a flat portion and a notch portion. In any of a first flat region and a first notch region, when an atomic concentration of sulfur is from 2.0×1018 to 8.0×1018 cm?3, the indium phosphide crystal substrate has an average dislocation density of 10-500 cm?2, and when an atomic concentration of tin is from 1.0×1015 to 4.0×1018 cm?3 or an atomic concentration of iron is from 5.0×1015 to 1.0×1017 cm?3, the indium phosphide crystal substrate has an average dislocation density of 500-5000 cm?2.
    Type: Application
    Filed: February 23, 2018
    Publication date: February 27, 2020
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Muneyuki NISHIOKA, Kazuaki KONOIKE, Takuya YANAGISAWA, Yasuaki HIGUCHI, Yoshiaki HAGI
  • Publication number: 20200041247
    Abstract: An indium phosphide substrate, a method of inspecting thereof and a method of producing thereof are provided, by which an epitaxial film grown on the substrate is rendered excellently uniform, thereby allowing improvement in PL characteristics and electrical characteristics of an epitaxial wafer formed using this epitaxial film. The indium phosphide substrate has a first main surface and a second main surface, a surface roughness Ra1 at a center position on the first main surface, and surface roughnesses Ra2, Ra3, Ra4, and Ra5 at four positions arranged equidistantly along an outer edge of the first main surface and located at a distance of 5 mm inwardly from the outer edge. An average value m1 of the surface roughnesses Ra1, Ra2, Ra3, Ra4, and Ra5 is 0.5 nm or less, and a standard deviation ?1 of the surface roughnesses Ra1, Ra2, Ra3, Ra4, and Ra5 is 0.2 nm or less.
    Type: Application
    Filed: August 14, 2019
    Publication date: February 6, 2020
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Shinya FUJIWARA, Yasuaki HIGUCHI
  • Patent number: 10473445
    Abstract: An indium phosphide substrate, a method of inspecting thereof and a method of producing thereof are provided, by which an epitaxial film grown on the substrate is rendered excellently uniform, thereby allowing improvement in PL characteristics and electrical characteristics of an epitaxial wafer formed using this epitaxial film. The indium phosphide substrate has a first main surface and a second main surface, a surface roughness Ra1 at a center position on the first main surface, and surface roughnesses Ra2, Ra3, Ra4, and Ra5 at four positions arranged equidistantly along an outer edge of the first main surface and located at a distance of 5 mm inwardly from the outer edge. An average value m1 of the surface roughnesses Ra1, Ra2, Ra3, Ra4, and Ra5 is 0.5 nm or less, and a standard deviation ?1 of the surface roughnesses Ra1, Ra2, Ra3, Ra4, and Ra5 is 0.2 nm or less.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: November 12, 2019
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shinya Fujiwara, Yasuaki Higuchi
  • Patent number: 10436566
    Abstract: An indium phosphide substrate, a method of inspecting thereof and a method of producing thereof are provided, by which an epitaxial film grown on the substrate is rendered excellently uniform, thereby allowing improvement in PL characteristics and electrical characteristics of an epitaxial wafer formed using this epitaxial film. The indium phosphide substrate has a first main surface and a second main surface, a surface roughness Ra1 at a center position on the first main surface, and surface roughnesses Ra2, Ra3, Ra4, and Ra5 at four positions arranged equidistantly along an outer edge of the first main surface and located at a distance of 5 mm inwardly from the outer edge. An average value m1 of the surface roughnesses Ra1, Ra2, Ra3, Ra4, and Ra5 is 0.5 nm or less, and a standard deviation ?1 of the surface roughnesses Ra1, Ra2, Ra3, Ra4, and Ra5 is 0.2 nm or less.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: October 8, 2019
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shinya Fujiwara, Yasuaki Higuchi
  • Publication number: 20190257002
    Abstract: A GaAs substrate has a first surface. The sum of the number of particles having a longer diameter of more than or equal to 0.16 ?m which are present in the first surface, per cm2 of the first surface, and the number of damages having a longer diameter of more than or equal to 0.16 ?m which are present in a second surface, per cm2 of the second surface, is less than or equal to 2.1, the second surface being formed by etching the first surface by 0.5 ?m in a depth direction.
    Type: Application
    Filed: May 26, 2017
    Publication date: August 22, 2019
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Shinya FUJIWARA, Yasuaki HIGUCHI
  • Publication number: 20170363406
    Abstract: An indium phosphide substrate, a method of inspecting thereof and a method of producing thereof are provided, by which an epitaxial film grown on the substrate is rendered excellently uniform, thereby allowing improvement in PL characteristics and electrical characteristics of an epitaxial wafer formed using this epitaxial film. The indium phosphide substrate has a first main surface and a second main surface, a surface roughness Ra1 at a center position on the first main surface, and surface roughnesses Ra2, Ra3, Ra4, and Ra5 at four positions arranged equidistantly along an outer edge of the first main surface and located at a distance of 5 mm inwardly from the outer edge. An average value m1 of the surface roughnesses Ra1, Ra2, Ra3, Ra4, and Ra5 is 0.5 nm or less, and a standard deviation ?1 of the surface roughnesses Ra1, Ra2, Ra3, Ra4, and Ra5 is 0.2 nm or less.
    Type: Application
    Filed: December 7, 2015
    Publication date: December 21, 2017
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Shinya FUJIWARA, Yasuaki HIGUCHI
  • Publication number: 20100013053
    Abstract: The present invention provides a method for manufacturing a III-V compound semiconductor substrate, a method for manufacturing an epitaxial wafer, a III-V compound semiconductor substrate, and an epitaxial wafer, wherein the thickness of an oxide film formed on the substrate or in the wafer is controlled with high precision, and surface of the epitaxial wafer is prevented from getting rough,. The method for manufacturing a III-V compound semiconductor substrate according to the present invention includes the following steps. Initially, a substrate composed of a III-V compound semiconductor is provided. Thereafter, the resulting substrate is cleaned with an acidic solution. Subsequently, an oxide film is formed on the substrate by a wet method after the cleaning.
    Type: Application
    Filed: July 8, 2009
    Publication date: January 21, 2010
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Masahiro NAKAYAMA, Yasuaki Higuchi
  • Patent number: 7619301
    Abstract: A GaAs semiconductor substrate includes a surface layer. When an atomic ratio is to be calculated using a 3d electron spectrum of Ga atoms and As atoms measured at the condition of 10° for the photoelectron take-off angle ? by X-ray photoelectron spectroscopy, the structural atomic ratio of all Ga atoms to all As atoms (Ga)/(As) at the surface layer is at least 0.5 and not more than 0.9, the ratio of As atoms bound with O atoms to all Ga atoms and all As atoms (As—O)/{(Ga)+(As)} at the surface layer is at least 0.15 and not more than 0.35, and the ratio of Ga atoms bound with O atoms to all Ga atoms and all As atoms (Ga—O)/{(Ga)+(As)} at the surface layer is at least 0.15 and not more than 0.35. Accordingly, there is provided a GaAs semiconductor substrate having a surface cleaned to an extent allowing removal of impurities and oxides at the surface by at least thermal cleaning of the substrate.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: November 17, 2009
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takayuki Nishiura, Yoshio Mezaki, Yusuke Horie, Yasuaki Higuchi
  • Publication number: 20080296738
    Abstract: A GaAs semiconductor substrate includes a surface layer. When an atomic ratio is to be calculated using a 3d electron spectrum of Ga atoms and As atoms measured at the condition of 10° for the photoelectron take-off angle ? by X-ray photoelectron spectroscopy, the structural atomic ratio of all Ga atoms to all As atoms (Ga)/(As) at the surface layer is at least 0.5 and not more than 0.9, the ratio of As atoms bound with O atoms to all Ga atoms and all As atoms (As—O)/{(Ga)+(As)} at the surface layer is at least 0.15 and not more than 0.35, and the ratio of Ga atoms bound with O atoms to all Ga atoms and all As atoms (Ga—O)/{(Ga)+(As)} at the surface layer is at least 0.15 and not more than 0.35. Accordingly, there is provided a GaAs semiconductor substrate having a surface cleaned to an extent allowing removal of impurities and oxides at the surface by at least thermal cleaning of the substrate.
    Type: Application
    Filed: October 9, 2007
    Publication date: December 4, 2008
    Inventors: Takayuki Nishiura, Yoshio Mezaki, Yusuke Horie, Yasuaki Higuchi