Patents by Inventor Yasuaki Yonemochi
Yasuaki Yonemochi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10748919Abstract: An annular dielectric spacer can be formed at a level of a joint-level dielectric material layer between vertically neighboring pairs of alternating stacks of insulating layers and spacer material layers. After formation of a memory opening through multiple alternating stacks and formation of a memory film therein, an anisotropic etch can be performed to remove a horizontal bottom portion of the memory film. The annular dielectric spacer can protect underlying portions of the memory film during the anisotropic etch. In addition, a silicon nitride barrier may be employed to suppress hydrogen diffusion at an edge region of peripheral devices.Type: GrantFiled: May 25, 2018Date of Patent: August 18, 2020Assignee: SANDISK TECHNOLOGY LLCInventors: Dai Iwata, Hiroyuki Ogawa, Kazutaka Yoshizawa, Yasuaki Yonemochi
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Publication number: 20180277566Abstract: An annular dielectric spacer can be formed at a level of a joint-level dielectric material layer between vertically neighboring pairs of alternating stacks of insulating layers and spacer material layers. After formation of a memory opening through multiple alternating stacks and formation of a memory film therein, an anisotropic etch can be performed to remove a horizontal bottom portion of the memory film. The annular dielectric spacer can protect underlying portions of the memory film during the anisotropic etch. In addition, a silicon nitride barrier may be employed to suppress hydrogen diffusion at an edge region of peripheral devices.Type: ApplicationFiled: May 25, 2018Publication date: September 27, 2018Inventors: Dai Iwata, Hiroyuki Ogawa, Kazutaka Yoshizawa, Yasuaki Yonemochi
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Patent number: 9991280Abstract: An annular dielectric spacer can be formed at a level of a joint-level dielectric material layer between vertically neighboring pairs of alternating stacks of insulating layers and spacer material layers. After formation of a memory opening through multiple alternating stacks and formation of a memory film therein, an anisotropic etch can be performed to remove a horizontal bottom portion of the memory film. The annular dielectric spacer can protect underlying portions of the memory film during the anisotropic etch. In addition, a silicon nitride barrier may be employed to suppress hydrogen diffusion at an edge region of peripheral devices.Type: GrantFiled: February 16, 2017Date of Patent: June 5, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Tadashi Nakamura, Jin Liu, Kazuya Tokunaga, Marika Gunji-Yoneoka, Matthias Baenninger, Hiroyuki Kinoshita, Murshed Chowdhury, Jiyin Xu, Dai Iwata, Hiroyuki Ogawa, Kazutaka Yoshizawa, Yasuaki Yonemochi
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Publication number: 20170236835Abstract: An annular dielectric spacer can be formed at a level of a joint-level dielectric material layer between vertically neighboring pairs of alternating stacks of insulating layers and spacer material layers. After formation of a memory opening through multiple alternating stacks and formation of a memory film therein, an anisotropic etch can be performed to remove a horizontal bottom portion of the memory film. The annular dielectric spacer can protect underlying portions of the memory film during the anisotropic etch. In addition, a silicon nitride barrier may be employed to suppress hydrogen diffusion at an edge region of peripheral devices.Type: ApplicationFiled: February 16, 2017Publication date: August 17, 2017Inventors: Tadashi NAKAMURA, Jin LIU, Kazuya TOKUNAGA, Marika GUNJI-YONEOKA, Matthias BAENNINGER, Hiroyuki KINOSHITA, Murshed CHOWDHURY, Jiyin XU, Dai IWATA, Hiroyuki OGAWA, Kazutaka YOSHIZAWA, Yasuaki YONEMOCHI
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Publication number: 20170025426Abstract: A NAND flash memory array includes a select line that is formed from a portion of a first conductive layer and a portion of second conductive layer separated by dielectric, and a connecting portion of a third conductive layer, the connecting portion extending in contact with a side of the portion of the first conductive layer and a side of the portion of the second conductive layerType: ApplicationFiled: July 24, 2015Publication date: January 26, 2017Inventors: Takatoshi Kano, Yasuaki Yonemochi, Kota Funayama
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Patent number: 9502428Abstract: A method of forming narrow and wide lines includes forming mandrels separated by wider gaps and narrower gaps, forming sidewall spacers on sides of the gaps, and then removing the mandrels. Subsequent anisotropic etching extends through an underlying mask layer at locations between sidewall spacers that were formed in wider gaps, to thereby separate narrow line portions of the mask layer, without extending through the mask layer at locations between sidewall spacers that were formed in narrower gaps, thereby leaving wide line portions of the mask layer under the second sidewall spacers.Type: GrantFiled: April 29, 2015Date of Patent: November 22, 2016Assignee: SanDisk Technologies LLCInventor: Yasuaki Yonemochi
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Publication number: 20160322371Abstract: A method of forming narrow and wide lines includes forming mandrels separated by wider gaps and narrower gaps, forming sidewall spacers on sides of the gaps, and then removing the mandrels. Subsequent anisotropic etching extends through an underlying mask layer at locations between sidewall spacers that were formed in wider gaps, to thereby separate narrow line portions of the mask layer, without extending through the mask layer at locations between sidewall spacers that were formed in narrower gaps, thereby leaving wide line portions of the mask layer under the second sidewall spacers.Type: ApplicationFiled: April 29, 2015Publication date: November 3, 2016Inventor: Yasuaki Yonemochi
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Patent number: 8669172Abstract: A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, a second insulation film formed on the second control gate to contact the first insulation film, and a gap portion formed at least between the first floating gate and the second floating gate by achieving contact between the first insulation film and the second insulation film are included. With this, a function of a nonvolatile semiconductor device can be ensured and a variation in a threshold voltage of a floating gate can be suppressed.Type: GrantFiled: June 4, 2012Date of Patent: March 11, 2014Assignee: Renesas Electronics CorporationInventors: Yasuaki Yonemochi, Hisakazu Otoi, Akio Nishida, Shigeru Shiratake
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Publication number: 20120238089Abstract: A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, a second insulation film formed on the second control gate to contact the first insulation film, and a gap portion formed at least between the first floating gate and the second floating gate by achieving contact between the first insulation film and the second insulation film are included. With this, a function of a nonvolatile semiconductor device can be ensured and a variation in a threshold voltage of a floating gate can be suppressed.Type: ApplicationFiled: June 4, 2012Publication date: September 20, 2012Applicant: Renesas Electronics CorporationInventors: Yasuaki YONEMOCHI, Hisakazu Otoi, Akio Nishida, Shigeru Shiratake
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Patent number: 8211777Abstract: A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, a second insulation film formed on the second control gate to contact the first insulation film, and a gap portion formed at least between the first floating gate and the second floating gate by achieving contact between the first insulation film and the second insulation film are included. With this, a function of a nonvolatile semiconductor device can be ensured and a variation in a threshold voltage of a floating gate can be suppressed.Type: GrantFiled: March 19, 2010Date of Patent: July 3, 2012Assignee: Renesas Electronics CorporationInventors: Yasuaki Yonemochi, Hisakazu Otoi, Akio Nishida, Shigeru Shiratake
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Publication number: 20100190330Abstract: A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, a second insulation film formed on the second control gate to contact the first insulation film, and a gap portion formed at least between the first floating gate and the second floating gate by achieving contact between the first insulation film and the second insulation film are included. With this, a function of a nonvolatile semiconductor device can be ensured and a variation in a threshold voltage of a floating gate can be suppressed.Type: ApplicationFiled: March 19, 2010Publication date: July 29, 2010Applicant: Renesas Technology Corp.Inventors: Yasuaki YONEMOCHI, Hisakazu Otoi, Akio Nishida, Shigeru Shiratake
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Patent number: 7705392Abstract: A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, a second insulation film formed on the second control gate to contact the first insulation film, and a gap portion formed at least between the first floating gate and the second floating gate by achieving contact between the first insulation film and the second insulation film are included. With this, a function of a nonvolatile semiconductor device can be ensured and a variation in a threshold voltage of a floating gate can be suppressed.Type: GrantFiled: April 13, 2006Date of Patent: April 27, 2010Assignee: Renesas Technology Corp.Inventors: Yasuaki Yonemochi, Hisakazu Otoi, Akio Nishida, Shigeru Shiratake
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Publication number: 20100044772Abstract: A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, a second insulation film formed on the second control gate to contact the first insulation film, and a gap portion formed at least between the first floating gate and the second floating gate by achieving contact between the first insulation film and the second insulation film are included. With this, a function of a nonvolatile semiconductor device can be ensured and a variation in a threshold voltage of a floating gate can be suppressed.Type: ApplicationFiled: November 5, 2009Publication date: February 25, 2010Applicant: RENESAS TECHNOLOGY CORP.Inventors: Yasuaki YONEMOCHI, Hisakazu OTOI, Akio NISHIDA, Shigeru SHIRATAKE
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Publication number: 20080303066Abstract: A semiconductor device is provided which can suppress the deterioration of its reliability caused by liquid soaking into a gap. The semiconductor device includes plural gate electrode layers and an interlayer insulating film. The gate electrode layers are formed so as to extend in the same direction in a planar layout and each have a gate wiring portion and a contact pad portion. The interlayer insulating film is formed over the gate electrode layers and gaps so as to leave the gaps each between adjacent gate wiring portions and also between adjacent gate wiring portion and contact pad portion. A second spacing which is the distance between adjacent gate wiring portion and contact pad portion is 2.1 times or less as large as a first spacing which is the distance between adjacent gate wiring portions.Type: ApplicationFiled: May 11, 2008Publication date: December 11, 2008Inventors: Yasuaki Yonemochi, Hisakazu Otoi
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Publication number: 20060231884Abstract: A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, a second insulation film formed on the second control gate to contact the first insulation film, and a gap portion formed at least between the first floating gate and the second floating gate by achieving contact between the first insulation film and the second insulation film are included. With this, a function of a nonvolatile semiconductor device can be ensured and a variation in a threshold voltage of a floating gate can be suppressed.Type: ApplicationFiled: April 13, 2006Publication date: October 19, 2006Inventors: Yasuaki Yonemochi, Hisakazu Otoi, Akio Nishida, Shigeru Shiratake