Abstract: This structural member (W1) is manufactured using a structural member manufacturing device including: a first clamping part (10) having a first lower clamping member (11) and a second upper clamping member (12) disposed to face each other and capable of being opened and closed; a second clamping part (20) having a third lower clamping member (21) and a fourth upper clamping member (22) disposed to face each other corresponding to the first lower clamping member (11) and the second upper clamping member (12) and capable of being opened and closed; and clamping part driving means for allowing the first clamping part (10) and the second clamping part (20) to be relatively separated from each other while causing a position in an X-axis direction and a position in a Z-axis direction to correspond to each other.

Abstract: Disclosed is a seat including: sensors which includes a first cushion sensor provided at a seat cushion in a position corresponding to buttocks of an occupant, a second cushion sensor provided at the seat cushion and located farther frontward than the first cushion sensor, a first back sensor provided at a seat back and located in a lower position thereof, and a second back sensor provided at the seat back and located above the first back sensor; and a controller connected to the sensors and thereby allowed to acquire pressure values from the respective sensors. The controller is configured to identify the motion of the occupant based on outputs of at least two sensors of the first cushion sensor, the second cushion sensor, the first back sensor, and the second back sensor.

Abstract: Provided are an apparatus and a method for biological treatment of an organic wastewater where it is possible to efficiently remove organic matter under high load while reducing the amount of air used for aerobic biological treatment and substantially decreasing the amount of sludge generated. The apparatus is provided with: a first biological treatment tank which has a fixed-type immobilized biocarrier and an aeration means; a second biological treatment tank to which a treated liquid from the first tank is introduced so as to perform treatment using suspended microorganisms, and which has an aeration means; and a sedimentation tank in which solid-liquid from the second tank is separated said liquid into settled sludge and treated water, wherein the apparatus has an influent line through which an organic wastewater is introduced to the first tank and the second tank, and a return line through which part of settled sludge discharged from the tank is returned to the tank.

Abstract: An apparatus includes an instruction issuer that issues an instruction; and a cache including a cache data memory and a cache tag including cache entries, and a cache controller configured to perform cache-hit judgement, in response to a memory-access instruction issued from the instruction issuer, based on an address of the memory-access instruction and configured to issue a memory-access request to a memory in a case where the cache-hit judgement is a cache miss, wherein the cache controller registers, when issuing the memory-access request, data obtained by the memory-access request in the cache data memory, and registers provisional registration information of a provisional registration state indicating that cache registration is performed by execution of a speculative memory-access instruction in the cache tag, and judges as a speculative entry cache miss and issues the memory-access request.

Abstract: An apparatus includes an instruction issuer that issues an instruction; and a cache including a cache data memory and a cache tag including cache entries, and a cache controller configured to perform cache-hit judgement, in response to a memory-access instruction issued from the instruction issuer, based on an address of the memory-access instruction and configured to issue a memory-access request to a memory in a case where the cache-hit judgement is a cache miss, wherein the cache controller registers, when issuing the memory-access request, data obtained by the memory-access request in the cache data memory, and registers provisional registration information of a provisional registration state indicating that cache registration is performed by execution of a speculative memory-access instruction in the cache tag, and judges as a speculative entry cache miss and issues the memory-access request.

Abstract: An object of the present invention is to provide a coffee beverage containing a milk component in which the precipitation generated by heat sterilization and/or upon storage of a coffee beverage containing a milk component is significantly inhibited by a simple method. The object can be attained by incorporating three components: an organic acid, an organic acid salt, and an organic-acid ester of monoglyceride, in a coffee beverage containing a milk component.

Abstract: An object of the present invention is to provide a dispersion stabilizer that has an effect of improving or stabilizing the dispersibility of solids insoluble in aqueous media and/or liquid components immiscible therewith. The above object can be achieved by a dispersion stabilizer comprising welan gum.

Abstract: A semiconductor memory includes a plurality of nonvolatile memory cells arranged in a matrix and coupled to control gate lines, selection gate lines, bit lines, and source lines, and includes a source line control unit. The source line control unit, at a time of program operation, sets one of the source lines coupled to a row of the memory cells including a program memory cell to a high level voltage, and sets at least one of the remaining source lines coupled to a row of a non-program memory cells to be higher than a low level voltage of the selection gate lines and to be lower than the high level voltage of an unselection bit line. Thereby, a leak current lowering a voltage of the source lines at the time of program operation can be blocked off, and a program operation time may be shortened.

Abstract: Disclosed herein is a micro TLB which includes a CAM section having a plurality of CAM circuits, each stores address information which represents correlation between a virtual address and a physical address; and a write control section which directs writing of the address information into each CAM circuit pointed by a write pointer, when a new address information is requested to be stored, wherein the micro TLB being configured to increment the write pointer, if the address information stored in each CAM circuit pointed by the write pointer has been used for address translation, so as to hold a recently-used address information while preventing the CAM circuit, having indication of use of the address information, from being overwritten with the new address information.

Abstract: A lithography process window analyzing method for setting a process window based on ranges of exposure amounts and focus positions, and giving evaluation of reliability of the set process window, includes setting, based on a plurality of process conditions including exposure amounts and focus positions in the performed exposure processing, analysis reliability M for process conditions including an arbitrary exposure amount and an arbitrary focus position; calculating reliability R of the process window based on the analysis reliability M concerning the process conditions included in the process window; and comparing a magnitude relation between the reliability R and a predetermined threshold and determining presence or absence of reliability of the process window according to a result of the comparison.

Abstract: A semiconductor memory includes a plurality of nonvolatile memory cells arranged in a matrix and coupled to control gate lines, selection gate lines, bit lines, and source lines, and includes a source line control unit. The source line control unit, at a time of program operation, sets one of the source lines coupled to a row of the memory cells including a program memory cell to a high level voltage, and sets at least one of the remaining source lines coupled to a row of a non-program memory cells to be higher than a low level voltage of the selection gate lines and to be lower than the high level voltage of an unselection bit line. Thereby, a leak current lowering a voltage of the source lines at the time of program operation can be blocked off, and a program operation time may be shortened.

Abstract: In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another. The second bus has a size larger than a size of the first bus.

Abstract: The present invention provides a method for enhancing a foam retention property of a beverage, and in addition a method for stably retaining foam in a beverage, the foam obtained by shaking the beverage, by enhancing the foam retention property. The present invention is implemented by preparing a beverage by using a fermentation-derived cellulose as a raw material thereof, more preferably by preparing a beverage by using a fermentation-derived cellulose in a state of complex with a high molecular substance.

Abstract: In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another. The second bus has a size larger than a size of the first bus.

Abstract: A lithography process window analyzing method for setting a process window based on ranges of exposure amounts and focus positions, and giving evaluation of reliability of the set process window, includes setting, based on a plurality of process conditions including exposure amounts and focus positions in the performed exposure processing, analysis reliability M for process conditions including an arbitrary exposure amount and an arbitrary focus position; calculating reliability R of the process window based on the analysis reliability M concerning the process conditions included in the process window; and comparing a magnitude relation between the reliability R and a predetermined threshold and determining presence or absence of reliability of the process window according to a result of the comparison.

Abstract: In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another. The second bus has a size larger than a size of the first bus.

Abstract: In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another. The second bus has a size larger than a size of the first bus.

Abstract: Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock.

Abstract: A semiconductor memory device has a burst write mode in which predetermined plural command signals are input through a plurality of command pads and a mask control operation in the burst write mode is performed in response to the command signals. Therefore, the mask control in burst write mode is increased in speed to give an improved data transfer rate.

Abstract: In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another. The second bus has a size larger than a size of the first bus.