Patents by Inventor Yasuhiko Kurosawa

Yasuhiko Kurosawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180210654
    Abstract: A semiconductor memory device includes a NAND memory including a plurality of blocks, each of which is a unit of data erasing, and a controller. The controller is configured to select an initial value from a group of initial values, based on an address of the NAND memory in which data are to be written, set a value corresponding to the selected initial value to a linear feedback shift register circuit, randomize the data using an output value of the linear feedback shift register circuit, and write the randomized data to the address of the NAND memory. A size of each of the blocks S is smaller than 2n-1 bytes, n being a number of registers included in the linear feedback shift register circuit.
    Type: Application
    Filed: March 19, 2018
    Publication date: July 26, 2018
    Inventors: Tsuyoshi ATSUMI, Yasuhiko KUROSAWA
  • Patent number: 10018673
    Abstract: According to one embodiment, a semiconductor device comprises an integrated circuit having a plurality of current modes different in operation current; a voltage sensor that detects a voltage in use by the integrated circuit; a BIST control circuit that generates BIST patterns different in the operation current and creates a flag indicating the success or failure of a BIST corresponding to the operation current based on the result of detecting the voltage while the integrated circuit is made to operate based on the BIST pattern; and a storing unit that stores the flag. The integrated circuit sets the current mode based on the flag.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: July 10, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yasuhiko Kurosawa
  • Patent number: 9928920
    Abstract: According to one embodiment, a temperature of a non-volatile memory or an ambient temperature of the non-volatile memory is acquired. A distribution of a threshold voltage, which is corrected according to the acquired temperature, is acquired from the non-volatile memory. Read voltages related to the reading of data are detected from the distribution. Error correction is performed for data read from the non-volatile memory, using the read voltages. The detected read voltages are separately corrected on the basis of the acquired temperature when the error correction has failed.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: March 27, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yasuhiko Kurosawa, Tsuyoshi Atsumi, Masanobu Shirakawa, Tokumasa Hara, Naoya Tokiwa
  • Patent number: 9921772
    Abstract: A semiconductor memory device includes a NAND memory including a plurality of blocks, each of which is a unit of data erasing, and a controller. The controller is configured to select an initial value from a group of initial values, based on an address of the NAND memory in which data are to be written, set a value corresponding to the selected initial value to a linear feedback shift register circuit, randomize the data using an output value of the linear feedback shift register circuit, and write the randomized data to the address of the NAND memory. A size of each of the blocks S is smaller than 2n?1 bytes, n being a number of registers included in the linear feedback shift register circuit.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: March 20, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Tsuyoshi Atsumi, Yasuhiko Kurosawa
  • Publication number: 20180074791
    Abstract: A randomizer includes a first pseudorandom number generator, a second pseudorandom number generator, and a first logic circuit configured to output a pseudorandom sequence by carrying out an operation on a pseudorandom sequence generated by the first pseudorandom number generator and a pseudorandom sequence generated by the second pseudorandom number generator, and a second logic circuit configured to randomize a data string input to the randomizer based on the pseudorandom sequence output by the first logic circuit.
    Type: Application
    Filed: March 2, 2017
    Publication date: March 15, 2018
    Inventors: Tsuyoshi ATSUMI, Yasuhiko KUROSAWA, Yohei KOGANEI, Yuji NAGAI
  • Publication number: 20170160939
    Abstract: A semiconductor memory device includes a NAND memory including a plurality of blocks, each of which is a unit of data erasing, and a controller. The controller is configured to select an initial value from a group of initial values, based on an address of the NAND memory in which data are to be written, set a value corresponding to the selected initial value to a linear feedback shift register circuit, randomize the data using an output value of the linear feedback shift register circuit, and write the randomized data to the address of the NAND memory. A size of each of the blocks S is smaller than 2n?1 bytes, n being a number of registers included in the linear feedback shift register circuit.
    Type: Application
    Filed: August 31, 2016
    Publication date: June 8, 2017
    Inventors: Tsuyoshi ATSUMI, Yasuhiko KUROSAWA
  • Patent number: 9653156
    Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory and a memory controller. The memory controller has a first signal generation section that generates a first signal related with a read voltage used for read operation of the nonvolatile semiconductor memory, a second signal generation section that generates a second signal that specifies the temperature coefficient used for the correction for temperature of the read voltage, and a first interface section that outputs the first signal, the second signal and a read command. The nonvolatile semiconductor memory has a word line, a memory cell array includes memory cells connected to the word line, and a second interface section that receives the first signal, the second signal and the read command.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: May 16, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masanobu Shirakawa, Tsuyoshi Atsumi, Hidetaka Tsuji, Tomoyuki Kantani, Hideaki Yamamoto, Yasuhiko Kurosawa
  • Patent number: 9625986
    Abstract: According to one embodiment, a semiconductor device includes: an integrated circuit that has a plurality of power consumption modes different in power consumption; a temperature detection circuit that detects temperature of the integrated circuit; a counter that measures time taken for temperature change in the integrated circuit; and a state machine that causes a state transition to take place in the integrated circuit based on the temperature detected by the temperature detection circuit and the time measured by the counter, wherein the integrated circuit selects the power consumption mode based on the state subjected to transition by the state machine.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: April 18, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiko Kurosawa, Shuuji Matsumoto
  • Publication number: 20170076810
    Abstract: According to one embodiment, a temperature of a non-volatile memory or an ambient temperature of the non-volatile memory is acquired. A distribution of a threshold voltage, which is corrected according to the acquired temperature, is acquired from the non-volatile memory. Read voltages related to the reading of data are detected from the distribution. Error correction is performed for data read from the non-volatile memory, using the read voltages. The detected read voltages are separately corrected on the basis of the acquired temperature when the error correction has failed.
    Type: Application
    Filed: December 21, 2015
    Publication date: March 16, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiko KUROSAWA, Tsuyoshi ATSUMI, Masanobu SHIRAKAWA, Tokumasa HARA, Naoya TOKIWA
  • Publication number: 20160266640
    Abstract: According to one embodiment, a semiconductor device includes: an integrated circuit that has a plurality of power consumption modes different in power consumption; a temperature detection circuit that detects temperature of the integrated circuit; a counter that measures time taken for temperature change in the integrated circuit; and a state machine that causes a state transition to take place in the integrated circuit based on the temperature detected by the temperature detection circuit and the time measured by the counter, wherein the integrated circuit selects the power consumption mode based on the state subjected to transition by the state machine.
    Type: Application
    Filed: August 3, 2015
    Publication date: September 15, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiko KUROSAWA, Shuuji MATSUMOTO
  • Publication number: 20160266199
    Abstract: According to one embodiment, a semiconductor device comprises an integrated circuit having a plurality of current modes different in operation current; a voltage sensor that detects a voltage in use by the integrated circuit; a BIST control circuit that generates BIST patterns different in the operation current and creates a flag indicating the success or failure of a BIST corresponding to the operation current based on the result of detecting the voltage while the integrated circuit is made to operate based on the BIST pattern; and a storing unit that stores the flag. The integrated circuit sets the current mode based on the flag.
    Type: Application
    Filed: September 9, 2015
    Publication date: September 15, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Yasuhiko KUROSAWA
  • Publication number: 20160247561
    Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory and a memory controller. The memory controller has a first signal generation section that generates a first signal related with a read voltage used for read operation of the nonvolatile semiconductor memory, a second signal generation section that generates a second signal that specifies the temperature coefficient used for the correction for temperature of the read voltage, and a first interface section that outputs the first signal, the second signal and a read command. The nonvolatile semiconductor memory has a word line, a memory cell array includes memory cells connected to the word line, and a second interface section that receives the first signal, the second signal and the read command.
    Type: Application
    Filed: May 14, 2015
    Publication date: August 25, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masanobu SHIRAKAWA, Tsuyoshi Atsumi, Hidetaka Tsuji, Tomoyuki Kantani, Hideaki Yamamoto, Yasuhiko Kurosawa
  • Patent number: 9190159
    Abstract: Each memory cell has a threshold voltage to distinguish a storage data item. A controller generates one of storage data items from one or more sets of reception data, stores the storage data item, randomizes data transmission for memory cells, instructs the cells to store the randomized data, uses read voltage candidates to read storage data from the cells, counts a distribution of voltages stored in the cells for each read voltage candidate, specifies a minimum read voltage candidate where a sum of the counting exceeds an expected number, and uses the specified candidate as a read voltage to distinguish a first storage data item corresponding to the expected number and an adjacent second storage data item.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: November 17, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yasuhiko Kurosawa
  • Patent number: 9129711
    Abstract: According to one embodiment, a semiconductor memory device includes memory cells each given one of threshold voltages to store data, and a controller configured to use read voltages to determine threshold voltages of the memory cells. The controller is configured to use voltages over a window to read data from the memory cells to determine distribution of the threshold voltages of the memory cells to estimate a read voltage. The controller is further configured to execute the estimation of a read voltage for each of the read voltages. The controller is further configured to use an estimated value of a first read voltage of the read voltages to determine a window for estimation of a second read voltage of the read voltages.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: September 8, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yasuhiko Kurosawa
  • Patent number: 9081711
    Abstract: An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: July 14, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kenta Yasufuku, Shigeaki Iwasa, Yasuhiko Kurosawa, Hiroo Hayashi, Seiji Maeda, Mitsuo Saito
  • Patent number: 8949572
    Abstract: An effective address cache memory includes a TLB effective page memory configured to retain entry data including an effective page tag of predetermined high-order bits of an effective address of a process, and output a hit signal when the effective page tag matches the effective page tag from a processor; a data memory configured to retain cache data with the effective page tag or a page offset as a cache index; and a cache state memory configured to retain a cache state of the cache data stored in the data memory, in a manner corresponding to the cache index.
    Type: Grant
    Filed: October 16, 2009
    Date of Patent: February 3, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiko Kurosawa, Shigeaki Iwasa, Seiji Maeda, Nobuhiro Yoshida, Mitsuo Saito, Hiroo Hayashi
  • Publication number: 20140269055
    Abstract: Each memory cell has a threshold voltage to distinguish a storage data item. A controller generates one of storage data items from one or more sets of reception data, stores the storage data item, randomizes data transmission for memory cells, instructs the cells to store the randomized data, uses read voltage candidates to read storage data from the cells, counts a distribution of voltages stored in the cells for each read voltage candidate, specifies a minimum read voltage candidate where a sum of the counting exceeds an expected number, and uses the specified candidate as a read voltage to distinguish a first storage data item corresponding to the expected number and an adjacent second storage data item.
    Type: Application
    Filed: July 22, 2013
    Publication date: September 18, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Yasuhiko KUROSAWA
  • Publication number: 20140245089
    Abstract: According to one embodiment, a semiconductor memory device includes memory cells each given one of threshold voltages to store data, and a controller configured to use read voltages to determine threshold voltages of the memory cells. The controller is configured to use voltages over a window to read data from the memory cells to determine distribution of the threshold voltages of the memory cells to estimate a read voltage. The controller is further configured to execute the estimation of a read voltage for each of the read voltages. The controller is further configured to use an estimated value of a first read voltage of the read voltages to determine a window for estimation of a second read voltage of the read voltages.
    Type: Application
    Filed: June 17, 2013
    Publication date: August 28, 2014
    Inventor: Yasuhiko KUROSAWA
  • Publication number: 20140164702
    Abstract: An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address.
    Type: Application
    Filed: November 26, 2013
    Publication date: June 12, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kenta Yasufuku, Shigeaki Iwasa, Yasuhiko Kurosawa, Hiroo Hayashi, Seiji Maeda, Mitsuo Saito
  • Patent number: 8607024
    Abstract: An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address.
    Type: Grant
    Filed: December 1, 2010
    Date of Patent: December 10, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenta Yasufuku, Shigeaki Iwasa, Yasuhiko Kurosawa, Hiroo Hayashi, Seiji Maeda, Mitsuo Saito