Abstract: A semiconductor memory device includes a NAND memory including a plurality of blocks, each of which is a unit of data erasing, and a controller. The controller is configured to select an initial value from a group of initial values, based on an address of the NAND memory in which data are to be written, set a value corresponding to the selected initial value to a linear feedback shift register circuit, randomize the data using an output value of the linear feedback shift register circuit, and write the randomized data to the address of the NAND memory. A size of each of the blocks S is smaller than 2n?1 bytes, n being a number of registers included in the linear feedback shift register circuit.

Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory and a memory controller. The memory controller has a first signal generation section that generates a first signal related with a read voltage used for read operation of the nonvolatile semiconductor memory, a second signal generation section that generates a second signal that specifies the temperature coefficient used for the correction for temperature of the read voltage, and a first interface section that outputs the first signal, the second signal and a read command. The nonvolatile semiconductor memory has a word line, a memory cell array includes memory cells connected to the word line, and a second interface section that receives the first signal, the second signal and the read command.

Abstract: According to one embodiment, a semiconductor device includes: an integrated circuit that has a plurality of power consumption modes different in power consumption; a temperature detection circuit that detects temperature of the integrated circuit; a counter that measures time taken for temperature change in the integrated circuit; and a state machine that causes a state transition to take place in the integrated circuit based on the temperature detected by the temperature detection circuit and the time measured by the counter, wherein the integrated circuit selects the power consumption mode based on the state subjected to transition by the state machine.

Abstract: According to one embodiment, a temperature of a non-volatile memory or an ambient temperature of the non-volatile memory is acquired. A distribution of a threshold voltage, which is corrected according to the acquired temperature, is acquired from the non-volatile memory. Read voltages related to the reading of data are detected from the distribution. Error correction is performed for data read from the non-volatile memory, using the read voltages. The detected read voltages are separately corrected on the basis of the acquired temperature when the error correction has failed.

Abstract: According to one embodiment, a semiconductor device comprises an integrated circuit having a plurality of current modes different in operation current; a voltage sensor that detects a voltage in use by the integrated circuit; a BIST control circuit that generates BIST patterns different in the operation current and creates a flag indicating the success or failure of a BIST corresponding to the operation current based on the result of detecting the voltage while the integrated circuit is made to operate based on the BIST pattern; and a storing unit that stores the flag. The integrated circuit sets the current mode based on the flag.

Abstract: According to one embodiment, a semiconductor device includes: an integrated circuit that has a plurality of power consumption modes different in power consumption; a temperature detection circuit that detects temperature of the integrated circuit; a counter that measures time taken for temperature change in the integrated circuit; and a state machine that causes a state transition to take place in the integrated circuit based on the temperature detected by the temperature detection circuit and the time measured by the counter, wherein the integrated circuit selects the power consumption mode based on the state subjected to transition by the state machine.

Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory and a memory controller. The memory controller has a first signal generation section that generates a first signal related with a read voltage used for read operation of the nonvolatile semiconductor memory, a second signal generation section that generates a second signal that specifies the temperature coefficient used for the correction for temperature of the read voltage, and a first interface section that outputs the first signal, the second signal and a read command. The nonvolatile semiconductor memory has a word line, a memory cell array includes memory cells connected to the word line, and a second interface section that receives the first signal, the second signal and the read command.

Abstract: Each memory cell has a threshold voltage to distinguish a storage data item. A controller generates one of storage data items from one or more sets of reception data, stores the storage data item, randomizes data transmission for memory cells, instructs the cells to store the randomized data, uses read voltage candidates to read storage data from the cells, counts a distribution of voltages stored in the cells for each read voltage candidate, specifies a minimum read voltage candidate where a sum of the counting exceeds an expected number, and uses the specified candidate as a read voltage to distinguish a first storage data item corresponding to the expected number and an adjacent second storage data item.

Abstract: According to one embodiment, a semiconductor memory device includes memory cells each given one of threshold voltages to store data, and a controller configured to use read voltages to determine threshold voltages of the memory cells. The controller is configured to use voltages over a window to read data from the memory cells to determine distribution of the threshold voltages of the memory cells to estimate a read voltage. The controller is further configured to execute the estimation of a read voltage for each of the read voltages. The controller is further configured to use an estimated value of a first read voltage of the read voltages to determine a window for estimation of a second read voltage of the read voltages.

Abstract: An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address.

Abstract: An effective address cache memory includes a TLB effective page memory configured to retain entry data including an effective page tag of predetermined high-order bits of an effective address of a process, and output a hit signal when the effective page tag matches the effective page tag from a processor; a data memory configured to retain cache data with the effective page tag or a page offset as a cache index; and a cache state memory configured to retain a cache state of the cache data stored in the data memory, in a manner corresponding to the cache index.

Abstract: Each memory cell has a threshold voltage to distinguish a storage data item. A controller generates one of storage data items from one or more sets of reception data, stores the storage data item, randomizes data transmission for memory cells, instructs the cells to store the randomized data, uses read voltage candidates to read storage data from the cells, counts a distribution of voltages stored in the cells for each read voltage candidate, specifies a minimum read voltage candidate where a sum of the counting exceeds an expected number, and uses the specified candidate as a read voltage to distinguish a first storage data item corresponding to the expected number and an adjacent second storage data item.

Abstract: According to one embodiment, a semiconductor memory device includes memory cells each given one of threshold voltages to store data, and a controller configured to use read voltages to determine threshold voltages of the memory cells. The controller is configured to use voltages over a window to read data from the memory cells to determine distribution of the threshold voltages of the memory cells to estimate a read voltage. The controller is further configured to execute the estimation of a read voltage for each of the read voltages. The controller is further configured to use an estimated value of a first read voltage of the read voltages to determine a window for estimation of a second read voltage of the read voltages.

Abstract: An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address.

Abstract: An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address.

Abstract: According to one embodiment, a semiconductor memory device includes a memory and a controller. The memory includes a plurality of memory cells each of which stores data when one of an n number of threshold voltages (n being a natural number not less than two) is set. The controller reads data from the memory. The controller reads data from the memory cells at each of the threshold voltages in a read operation that checks a distribution of threshold voltages of the memory cells, calculates difference data on data read at each of the threshold voltages, calculates a minimum value of the distribution of the threshold voltages from the difference data, calculates a range of threshold voltages lower than the minimum value based on the minimum value, and sets a central voltage in the calculated range of threshold voltages as a read voltage.

Abstract: An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address.

Abstract: Systems and methods for increasing the yield of devices incorporating set-associative cache memories by selectively avoiding the use of cache entries that include defects. In one embodiment, a cache replacement manager determines in which of n possible entries data will be replaced. The cache replacement manager is configured to take into account whether each cache entry is defective when determining whether to select that entry as the destination entry for new data. The cache manager unit may implement a least-recently-used policy in selecting the cache entry in which the new data will be replaced. The cache replacement manager then treats any defective entries as if they hold the most recently used data, and thereby avoids selecting defective entries as the destination for new data. In one embodiment, the cache performs index translation before indexing into each set of cache entries in order to effectively redistribute defective entries among the indices.

Abstract: Systems and methods for increasing the efficiency of communications between master devices and slave devices in a system. A master normally sends a command to a slave if a token from the slave is received. Determining whether a token is of the correct type requires multiple processing cycles. Alternatively, if all of the slaves have available buffer slots, an “all token available” signal is asserted. When the “all token available” signal is received, the master can send any command without having to decode any of the tokens.

Abstract: A set associative cache memory includes a tag memory configured to store tags which are predetermined high-order bits of an address, a tag comparator configured to compare a tag in a request address (RA) with the tag stored in the tag memory and a data memory configured to incorporate way information obtained through a comparison by the tag comparator in part of a column address.