Patents by Inventor Yasuhiko Nara

Yasuhiko Nara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11391756
    Abstract: As a semiconductor device is miniaturized, a scribe area on a wafer also tends to decrease. Accordingly, it is necessary to reduce the size of a TEG arranged in the scribe area, and efficiently arrange an electrode pad for probe contact. Therefore, it is necessary to associate probes and the efficient layout of the electrode pad. The purpose of the present invention is to provide a technique for associating probes and the layout of an electrode pad of a TEG to facilitate the evaluation of electrical characteristics. According to the present invention, the above described problem can be solved by arranging a plurality of probes in a fan shape or manufacturing the probes with micro electro mechanical systems (MEMS) technology.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: July 19, 2022
    Assignee: Hitachi High-Tech Corporation
    Inventors: Ryo Hirano, Takayuki Mizuno, Tomohisa Ohtaki, Toru Fujimura, Shigehiko Kato, Yasuhiko Nara, Katsuo Ohki, Akira Kageyama, Masaaki Komori
  • Publication number: 20210048450
    Abstract: As a semiconductor device is miniaturized, a scribe area on a wafer also tends to decrease. Accordingly, it is necessary to reduce the size of a TEG arranged in the scribe area, and efficiently arrange an electrode pad for probe contact. Therefore, it is necessary to associate probes and the efficient layout of the electrode pad. The purpose of the present invention is to provide a technique for associating probes and the layout of the electrode pads of a TEG so as to facilitate the evaluation of electrical characteristics. According to a method for manufacturing a semiconductor device of the present invention, the above-described problems can be solved by providing a layout of a TEG electrode pad corresponding to a plurality of probes arranged in a fan shape or probes manufactured by Micro Electro Mechanical Systems (MEMS) technology.
    Type: Application
    Filed: February 6, 2018
    Publication date: February 18, 2021
    Inventors: Tomohisa OHTAKI, Takayuki MIZUNO, Ryo HIRANO, Toru FUJIMURA, Shigehiko KATO, Yasuhiko NARA, Katsuo OHKI, Akira KAGEYAMA, Masaaki KOMORI
  • Publication number: 20210033642
    Abstract: As a semiconductor device is miniaturized, a scribe area on a wafer also tends to decrease. Accordingly, it is necessary to reduce the size of a TEG arranged in the scribe area, and efficiently arrange an electrode pad for probe contact. Therefore, it is necessary to associate probes and the efficient layout of the electrode pad. The purpose of the present invention is to provide a technique for associating probes and the layout of an electrode pad of a TEG to facilitate the evaluation of electrical characteristics. According to the present invention, the above described problem can be solved by arranging a plurality of probes in a fan shape or manufacturing the probes with micro electro mechanical systems (MEMS) technology.
    Type: Application
    Filed: February 6, 2018
    Publication date: February 4, 2021
    Inventors: Ryo HIRANO, Takayuki MIZUNO, Tomohisa OHTAKI, Toru FUJIMURA, Shigehiko KATO, Yasuhiko NARA, Katsuo OHKI, Akira KAGEYAMA, Masaaki KOMORI
  • Publication number: 20210025936
    Abstract: As a semiconductor device is miniaturized, a scribe area on a wafer also tends to decrease. Accordingly, it is necessary to reduce the size of a TEG arranged in the scribe area, and efficiently arrange an electrode pad for probe contact. Therefore, it is necessary to associate probes and the efficient layout of the electrode pad. The purpose of the present invention is to provide a technique for associating probes and the layout of the electrode pads of a TEG so as to facilitate the evaluation of electrical characteristics. According to an evaluation apparatus for a semiconductor device of the present invention, the above described problems can be solved by providing a plurality of probes arranged in a fan shape or probes manufactured by Micro Electro Mechanical Systems (MEMS) technology.
    Type: Application
    Filed: February 6, 2018
    Publication date: January 28, 2021
    Inventors: Tomohisa OHTAKI, Takayuki MIZUNO, Ryo HIRANO, Toru FUJIMURA, Shigehiko KATO, Yasuhiko NARA, Katsuo OHKI, Akira KAGEYAMA, Masaaki KOMORI
  • Patent number: 10782340
    Abstract: The present invention relates to a prober device that shapes an input waveform of a dynamic electric signal to be input to one of probes, and observes an output waveform of the dynamic electric signal output through a sample, or preferably shapes the input waveform such that the output waveform of the dynamic electric signal output through the sample becomes approximately a pulse shape, when a response analysis of a dynamic signal is performed with respect to a fine-Structured device. With this, the response analysis of a high-speed dynamic signal equal to or greater than a megahertz level can be performed with respect to the fine-Structured device such as a minute transistor configuring an LSI.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: September 22, 2020
    Assignee: Hitachi High-Tech Corporation
    Inventors: Masaaki Komori, Katsuo Oki, Yasuhiko Nara, Takayuki Mizuno
  • Patent number: 10712384
    Abstract: An object of the present invention relates to detecting a signal caused by a faulty point part of which the identification has been difficult with conventional EBAC. In an embodiment of the present invention, at least one probe is brought into contact with a sample on which a circuit is formed, the sample is scanned with a charged particle beam while power is supplied via the probe to the circuit identified by a contact of the probe, and a change in resistance value of a faulty point heated locally is measured via the probe. According to the present invention, even a signal caused by a high-resistance faulty point or a faulty point embedded in the sample can be easily detected.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: July 14, 2020
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventors: Akira Kageyama, Yasuhiko Nara
  • Publication number: 20190062878
    Abstract: An aluminum alloy substrate for a magnetic recording medium, the substrate including: Si in a range of 9.5 to 13.0% by mass or less and Cu in a range of 0.5 to 3.0% by mass or less, wherein a content of Fe is less than 0.01% by mass, the balance is Al, the substrate has a diameter in a range of 53 to 97 mm and a thickness in a range of 0.4 to 0.9 mm or less, and the substrate satisfies at least one of the following conditions (i) and (ii): (i) Sr is contained in the substrate in a range of 0.005% by mass or more and 0.1% by mass or less; and (ii) at least a part of the Si is present as Si particles, and an average particle diameter of particles having a longest diameter of 0.5 ?m or more among the Si particles is 2 ?m or less.
    Type: Application
    Filed: August 20, 2018
    Publication date: February 28, 2019
    Applicant: SHOWA DENKO K.K.
    Inventors: Isao MURASE, Kiminori SUGIMOTO, Yasuhiko NARA, Yoshikazu KATO
  • Publication number: 20180299504
    Abstract: The present invention relates to a prober device that shapes an input waveform of a dynamic electric signal to be input to one of probes, and observes an output waveform of the dynamic electric signal output through a sample, or preferably shapes the input waveform such that the output waveform of the dynamic electric signal output through the sample becomes approximately a pulse shape, when a response analysis of a dynamic signal is performed with respect to a fine-Structured device. With this, the response analysis of a high-speed dynamic signal equal to or greater than a megahertz level can be performed with respect to the fine-Structured device such as a minute transistor configuring an LSI.
    Type: Application
    Filed: July 7, 2016
    Publication date: October 18, 2018
    Applicant: Hitachi High-Technologies Corporation
    Inventors: Masaaki KOMORI, Katsuo OKI, Yasuhiko NARA, Takayuki MIZUNO
  • Publication number: 20180246166
    Abstract: An object of the present invention relates to detecting a signal caused by a faulty point part of which the identification has been difficult with conventional EBAC. In an embodiment of the present invention, at least one probe is brought into contact with a sample on which a circuit is formed, the sample is scanned with a charged particle beam while power is supplied via the probe to the circuit identified by a contact of the probe, and a change in resistance value of a faulty point heated locally is measured via the probe. According to the present invention, even a signal caused by a high-resistance faulty point or a faulty point embedded in the sample can be easily detected.
    Type: Application
    Filed: July 22, 2016
    Publication date: August 30, 2018
    Inventors: Akira KAGEYAMA, Yasuhiko NARA
  • Patent number: 8816712
    Abstract: An object of the invention is to provide an inspection device which has a function of preventing electric discharge so that an absorbed current is detected more efficiently. In the invention, absorbed current detectors are mounted in a vacuum specimen chamber and capacitance of a signal wire from each probe to corresponding one of the absorbed current detectors is reduced to the order of pF so that even an absorbed current signal with a high frequency of tens of kHz or higher can be detected. Moreover, signal selectors are operated by a signal selection controller so that signal lines of a semiconductor parameters analyzer are electrically connected to the probes brought into contact with a sample. Accordingly, electrical characteristics of the sample can be measured without limitation of signal paths connected to the probes to transmission of an absorbed current. In addition, a resistance for slow leakage of electric charge is provided in each probe stage or a sample stage.
    Type: Grant
    Filed: July 29, 2009
    Date of Patent: August 26, 2014
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Mitsuhiro Nakamura, Hiroshi Toyama, Yasuhiko Nara, Katsuo Oki, Tomoharu Obuki, Masahiro Sasajima
  • Patent number: 8754664
    Abstract: The high magnification, high resolution and real-time property of an SEM image are realized when the electrical characteristics of an inspection object are measured, without affecting the electrical characteristics of the inspection object. A high-quality, high-magnification first image including an image of a target position in the inspection object on a sample is acquired. Next, a low-quality, low-magnification second image including the image of the target position in the inspection object on the sample and probe images is acquired. Next, data on the first image is built into the second image to generate an image for coarse-access observation which is the same in magnification as the second image. The generation of the image for coarse-access observation is repeated until a probe comes close to the target position in the inspection object.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: June 17, 2014
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Yasuhiko Nara, Tohru Ando
  • Publication number: 20130119999
    Abstract: Proposed is a technique of emphasizing a change in absorbed current obtained from a faulty part in a wiring section as a testing target more than in other parts of the wiring section. A specimen testing device is configured to output an image of absorbed current output from two probes during scanning of an electron beam so as to be operatively associated with the scanning of the electron beam and includes the following mechanism. When a faulty part of a wiring section on the specimen side with which two probes are in contact is irradiated with an electron beam, the resistance value at the faulty part changes more than that of irradiation of a normal wiring section with the electron beam. Such a change in resistance value is detected as a change in ratio between a resistance value of the wiring section specified by the two probes and a known resistance value.
    Type: Application
    Filed: July 20, 2011
    Publication date: May 16, 2013
    Applicant: Hitachi High-Technologies Corporation
    Inventors: Tomoharu Obuki, Mitsuhiro Nakamura, Yasuhiko Nara, Tohru Ando
  • Publication number: 20130112871
    Abstract: The high magnification, high resolution and real-time property of an SEM image are realized when the electrical characteristics of an inspection object are measured, without affecting the electrical characteristics of the inspection object. A high-quality, high-magnification first image including an image of a target position in the inspection object on a sample is acquired. Next, a low-quality, low-magnification second image including the image of the target position in the inspection object on the sample and probe images is acquired. Next, data on the first image is built into the second image to generate an image for coarse-access observation which is the same in magnification as the second image. The generation of the image for coarse-access observation is repeated until a probe comes close to the target position in the inspection object.
    Type: Application
    Filed: July 27, 2011
    Publication date: May 9, 2013
    Inventors: Yasuhiko Nara, Tohru Ando
  • Patent number: 8178837
    Abstract: A navigation system for easily determining defective positions is provided. In the case of CAD navigation to defective positions, logical information for indicating defective positions is created in a CAD format, instead of CAD data of physical information indicating circuit design. Specifically, by attaching marks such as rectangles, characters, or lines, to an electron microscope image with software, quick navigation is performed with required minimum information. By using created CAD data, re-navigation with the same equipment and CAD navigation to heterogeneous equipment are performed.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: May 15, 2012
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Tohru Ando, Tsutomu Saito, Yasuhiko Nara, Mikio Takagi, Koichi Takauchi
  • Patent number: 8178840
    Abstract: An object of the present invention is to obtain a clear absorbed current image without involving the difference in gain of amplifier between inputs, from absorbed currents detected by using a plurality of probes and to improve measurement efficiency. In the present invention, a plurality of probes are brought in contact with a specimen. While irradiating the specimen with an electron beam, currents flowing in the probes are measured. Signals from at least two probes are input to a differential amplifier. An output of the differential amplifier is amplified. On the basis of the amplified output and scanning information of the electron beam, an absorbed current image is generated. According to the invention, a clear absorbed current image can be obtained without involving the difference in gain of amplifier between inputs. Thus, measurement efficiency in a failure analysis of a semiconductor device can be improved.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: May 15, 2012
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Tomoharu Obuki, Hiroshi Toyama, Yasuhiro Mitsui, Munetoshi Fukui, Yasuhiko Nara, Tohru Ando, Katsuo Ooki, Tsutomu Saito, Masaaki Komori
  • Patent number: 8067752
    Abstract: A semiconductor testing method capable of quickly counting semiconductor cells in which a seemingly horizontal or vertical line is drawn with a mouse, and raster rotation is performed in alignment with the closer axis. After that, the stage is horizontally moved, pattern matching is performed on an image on a position where the image should be disposed, and an angle is adjusted. The stage is moved evenly along the X-axis and the Y-axis, achieving a movement to a destination like a straight line. In synchronization with the smooth movement of the stage, a cell is surrounded in a rectangular frame by a ruler, and the number of cells is displayed with a numeric value.
    Type: Grant
    Filed: April 22, 2010
    Date of Patent: November 29, 2011
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Tohru Ando, Yasuhiko Nara, Tsutomu Saito, Shinichi Kato, Takeshi Sunaoshi
  • Patent number: 7989766
    Abstract: A sample inspection apparatus in which a fault in a semiconductor sample can be measured and analyzed efficiently. A plurality of probes are brought into contact with the sample. The sample is irradiated with an electron beam while a current flowing through the probes is measured. Signals from at least two probes are supplied to an image processing unit so as to form an absorbed electron current image. A difference between images obtained in accordance with a temperature change of the sample is obtained. A faulty point is identified from the difference between the images.
    Type: Grant
    Filed: April 1, 2009
    Date of Patent: August 2, 2011
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Yasuhiko Nara, Tohru Ando, Masahiro Sasajima, Tsutomu Saito, Tomoharu Obuki, Isamu Sekihara
  • Publication number: 20110140729
    Abstract: An object of the invention is to provide an inspection device which has a function of preventing electric discharge so that an absorbed current is detected more efficiently. In the invention, absorbed current detectors are mounted in a vacuum specimen chamber and capacitance of a signal wire from each probe to corresponding one of the absorbed current detectors is reduced to the order of pF so that even an absorbed current signal with a high frequency of tens of kHz or higher can be detected. Moreover, signal selectors are operated by a signal selection controller so that signal lines of a semiconductor parameters analyzer are electrically connected to the probes brought into contact with a sample. Accordingly, electrical characteristics of the sample can be measured without limitation of signal paths connected to the probes to transmission of an absorbed current. In addition, a resistance for slow leakage of electric charge is provided in each probe stage or a sample stage.
    Type: Application
    Filed: July 29, 2009
    Publication date: June 16, 2011
    Applicant: Hitachi High-Technologies Corporation
    Inventors: Mitsuhiro Nakamura, Hiroshi Toyama, Yasuhiko Nara, Katsuo Oki, Tomoharu Obuki, Masahiro Sasajima
  • Patent number: 7957579
    Abstract: An apparatus for processing a defect candidate image, including: a scanning electron microscope for taking an enlarged image of a specimen by irradiating and scanning a converged electron beam onto the specimen and detecting charged particles emanated from the specimen by the irradiation; an image processor for processing the image taken by the scanning electron microscope to detect defect candidates on the specimen and classify the detected defect candidates into one of plural classes; a memory for storing output from the image processor including images of the detected defect candidates; and a display unit which displays information stored in the memory and an indicator, wherein the display unit displays a distribution of the detected and classified defect candidates in a map format by distinguishing by the classified class, and the display unit also displays an image of a defect candidate stored in the memory together with the map which is indicated on the map by the indicator.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: June 7, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Hiroi, Masahiro Watanabe, Chie Shishido, Aritoshi Sugimoto, Maki Tanaka, Hiroshi Miyai, Asahiro Kuni, Yasuhiko Nara
  • Patent number: D637098
    Type: Grant
    Filed: April 26, 2010
    Date of Patent: May 3, 2011
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Mitsuru Oonuma, Akira Omachi, Kazuhiko Nishiyama, Hiroyuki Suzuki, Yasuhiko Nara