Abstract: A driver circuit drives a write element for magnetic recording, and permits high speed recording while preventing noise from entering an adjacent read element. An H bridge circuit, which causes a write current to flow, in accordance with a write drive signal, in a write coil of the write element, is provided with an overshoot circuit, in which positive and negative power sources are of the same potential. It makes a flyback voltage vertically symmetrical. Further, a feedback circuit is provided which monitors the voltages at both ends of the write coil, and prevents a variation in the common potential of the write coil. Terminal resistors are further provided to prevent the effects of reflection in a transmission line, and to prevent a change in the write waveform.

Abstract: We identified a novel protein (Gm1) comprising an amino acid sequence part having a high homology with a domain having a high homology with a GTP binding site and a GTPase site conserved among G protein ? subunits and a trimer forming domain conserved among G protein ? subunits. The Gm1 is involved in an signal transduction via a G protein-coupled receptor (GPCR) stimulation. Accordingly, this protein is considered to be a novel G protein. The Gm1 is expressed intensively in human brain, thymus, testes, spleen, small intestine, uterus and heart. We also established a method for screening for a substance capable of regulating a cellular signal transduction employing a polynucleotide encoding the Gm1.

Abstract: A magnetic storage device equipped with a write driver circuit is provided. This magnetic storage device includes: four current sources each provided at a corresponding one of the four sides of an “H-bridge” circuit; a magnetic head provided at the bridging part of the “H-bridge” circuit; and a series circuit including capacitors and terminating resistors. A separate series circuit is provided between the ground and each corresponding one of the connection points of the bridging part and the four sides of the “H-bridge” circuit. With this magnetic storage device, impedance matching can be easily performed. Also, a smaller circuit size can be realized, and accordingly, the power consumption can be reduced. Furthermore, desired recording can be performed at a high transfer rate.

Abstract: An input interface circuit is provided which includes an input transistor for receiving a digital input signal, a circuit for generating a reference value, and an integrating capacitor connected in series to a pair of current conducting electrodes of the input transistor for integrating the input signal. A logic level of the input signal is discriminated by comparing an integration of the input signal with the reference value. To provide a testing function, a test transistor is connected to a junction between the pair of current conducting electrodes of the input transistor and the integrating capacitor so that a current driving capability may be determined. Additionally, a discharge path circuit for controllably discharging the integrating capacitor is connected to the junction between the input transistor and the integrating capacitor.

Abstract: A plurality of sets of circuits are provided, each of which generates an impedance code through the use of an impedance control circuit in association with a resistive element connected to an external terminal, and each of which varies the impedance in accordance with such an impedance code. The impedance control circuit includes an impedance comparator which is formed equivalently to the resistive element and the plurality of sets of circuits, and which performs an impedance comparison with each of a plurality of replica circuits to form an up signal that increases the impedance and a down signal that decreases the impedance. Counters are provided adjacent to the individuals of the plurality of sets of circuits to thereby generate the impedance codes in response to the up signal and the down signal.

Abstract: To provide a semiconductor memory device which has high speed operation and multifunctionality, and is suitable for 3D imaging. Data is output to a data terminal in synchronism with a synchronization signal during data read, write data is input via the data terminal in synchronism with a synchronization signal during data write, input of write data via the data terminal is permitted via the data terminal in a first period wherein output of read data to the data terminal should be performed, a second period is provided from when a write specification is issued to when input of write data starts, and a third period is provided during which input of write data is performed.

Abstract: An input interface circuit is provided. The circuit includes an input transistor for receiving a digital input signal, a circuit for generating a reference value, and an integrating capacitor connected in series to a pair of current conducting electrodes of the input transistor for integrating the input signal. A logic level of the input signal is discriminated by comparing an integration of the input signal with the reference value. To provide a testing function, a test transistor is connected to a junction between the pair of current conducting electrodes of the input transistor and the integrating capacitor so that a current driving capability may be determined. Additionally, a discharge path circuit for controllably discharging the integrating capacitor is connected to the junction between the input transistor and the integrating capacitor.

Abstract: The present invention provides a semiconductor memory device. In the semiconductor device, third and fourth transistors are configured as a vertical structure. The third transistor is laminated over a first transistor, and the fourth transistor is laminated over a second transistor, whereby a reduction in cell area is achieved. A voltage set on the condition that the difference between a source potential applied to each of the first and second transistors and the potential of a select level of a word line becomes greater than or equal to a threshold voltage of each of the third and fourth transistors, is supplied to a source electrode of each of the first and second transistors to thereby perform “0” write compensation.

Abstract: An electronic circuit device has a high-density mount board (2), on which are disposed a microcomputer (3) and random access memory (7) which are connected to each other through an exclusive memory bus (12) for high-speed data transfer, a programmable device (8) which is a variable logic circuit represented by FPGA, and an electrically-rewritable nonvolatile memory (16) which can store the operation program of the microcomputer. The high-density mount board has external mounting pins on the bottom surface so that it can be mounted on a mother board in the same manner as a system on-chip multi-chip module. With an intended logic function being set on the programmable device, a hardware-based function to be realized by the electronic circuit device can be simulated. With an operation program being written to the nonvolatile memory, a software-based function to be realized can be simulated.

Abstract: A magnetic storage device equipped with a write driver circuit is provided. This magnetic storage device includes: four current sources each provided at a corresponding one of the four sides of an “H-bridge” circuit; a magnetic head provided at the bridging part of the “H-bridge” circuit; and a series circuit including capacitors and terminating resistors. A separate series circuit is provided between the ground and each corresponding one of the connection points of the bridging part and the four sides of the “H-bridge” circuit. With this magnetic storage device, impedance matching can be easily performed. Also, a smaller circuit size can be realized, and accordingly, the power consumption can be reduced. Furthermore, desired recording can be performed at a high transfer rate.

Abstract: An electric current for writing low-frequency test data, or a direct current is applied to a magnetic recording head at a time point when data is not actually recorded, and a proper/improper operation of the magnetic recording head is detected by determining whether or not the terminal voltage of the head is within a predetermined range.

Abstract: A memory cell of a SRAM comprises two drive MISFET and two vertical MISFETs. The p channel vertical MISFET are formed above the n channel drive MISFET. The vertical MISFETs respectively mainly comprise a square pole laminate comprising a lower semiconductor layer, intermediate semiconductor layer and upper semiconductor layer laminated in this sequence, a gate insulating film comprising silicon oxide formed on the surface of the side wall of the laminate, and a gate electrode formed so as to cover the side wall of the laminate. The vertical MISFETs are perfect depletion type MISFETs.

Abstract: To provide a semiconductor memory device which has high speed operation and multifunctionality, and is suitable for 3D imaging. Data is output to a data terminal in synchronism with a synchronization signal during data read, write data is input via the data terminal in synchronism with a synchronization signal during data write, input of write data via the data terminal is permitted via the data terminal in a first period wherein output of read data to the data terminal should be performed, a second period is provided from when a write specification is issued to when input of write data starts, and a third period is provided during which input of write data is performed.

Abstract: A driver circuit drives a write element for magnetic recording, and permits high speed recording while preventing noise from entering an adjacent read element. An H bridge circuit, which causes a write current to flow, in accordance with a write drive signal, in a write coil of the write element, is provided with an overshoot circuit, in which positive and negative power sources are of the same potential. It makes a flyback voltage vertically symmetrical. Further, a feedback circuit is provided which monitors the voltages at both ends of the write coil, and prevents a variation in the common potential of the write coil. Terminal resistors are further provided to prevent the effects of reflection in a transmission line, and to prevent a change in the write waveform.

Abstract: To provide a semiconductor memory device which has high speed operation and multifunctionality, and is suitable for 3D imaging. Data is output to a data terminal in synchronism with a synchronization signal during data read, write data is input via the data terminal in synchronism with a synchronization signal during data write, input of write data via the data terminal is permitted via the data terminal in a first period wherein output of read data to the data terminal should be performed, a second period is provided from when a write specification is issued to when input of write data starts, and a third period is provided during which input of write data is performed.

Abstract: In an high-frequency LSI chip, a clock signal generating circuit which establish accurate synchronism between an input clock signal and an internal clock signal to prevent an input circuit to cause a synchronization shift. The clock signal generating circuit includes an input circuit for amplifying an input signal and outputting an amplified signal as a first internal signal; a variable delay circuit, on the basis of a control signal, for delaying the first internal signal and outputting a delayed signal as a second internal signal; a phase comparator for finding a phase difference between the input signal and second internal signal and outputting a phase difference signal indicative of the phase difference; and a control circuit for generating the control signal on the basis of the phase difference signal. Thereby the influences of a delay caused by the input circuit, which would not be able to be avoided in the prior art, can be avoided and thus the accurate internal clock signal can be generated.

Abstract: A signal processing circuit of a spin-valve magnetic sensor includes a polarity detection circuit for detecting a polarity of an output signal produced by the magnetic sensor and a polarity control unit controlling the polarity of the output signal in response to a result of the polarity detection.

Abstract: A main anode and a pilot anode are mounted on a coating film of a metal structure, a cathode is mounted on a metal based material of the metal structure, a predetermined voltage is applied from the pilot anode to the metal structure, a magnitude of corrosion protection current of the metal structure is read from a current value of the pilot anode varying with variation of corrosion environment of the metal structure, the application voltage of the main anode is increased or decreased in accordance with the current value, whereby providing a cathodic protection method and apparatus for a metal structure capable of expanding protectable area by a single anode to a maximum without causing over-corrosion protection.

Abstract: An input interface circuit is provided. The circuit includes an input transistor for receiving a digital input signal, a circuit for generating a reference value, and an integrating capacitor connected in series to a pair of current conducting electrodes of the input transistor for integrating the input signal. A logic level of the input signal is discriminated by comparing an integration of the input signal with the reference value. To provide a testing function, a test transistor is connected to a junction between the pair of current conducting electrodes of the input transistor and the integrating capacitor so that a current driving capability may be determined. Additionally, a discharge path circuit for controllably discharging the integrating capacitor is connected to the junction between the input transistor and the integrating capacitor.

Abstract: An input interface circuit is provided with an input transistor for receiving a digital input signal, a circuit for generating a reference value, and an integrating capacitor connected in series to a pair of current conducting electrodes of the input transistor for integrating the input signal, a logical level of the input signal being discriminated by comparing an integration of the input signal with the reference value. For a testing function mode, a test transistor is connected to a junction between the pair of current conducting electrodes of the input transistor and the integrating capacitor so that a current driving capability is determined. Also, a discharge path circuit for controllably discharging the integrating capacitor is connected to the junction between the input transistor and the integrating capacitor.