Patents by Inventor Yasuhiko Takahshi

Yasuhiko Takahshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor memory device and a method of manufacturing the same, a method of manufacturing a vertical MISFET and a vertical MISFET, and a method of manufacturing a semiconductor device and a semiconductor device
    Patent number: 8476138
    Abstract: Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: July 2, 2013
    Assignees: Hitachi ULSI Systems Co., Ltd., Renesas Electronics Corporation
    Inventors: Hiraku Chakihara, Kousuke Okuyama, Masahiro Moniwa, Makoto Mizuno, Keiji Okamoto, Mitsuhiro Noguchi, Tadanori Yoshida, Yasuhiko Takahshi, Akio Nishida
  • SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF MANUFACTURING THE SAME, A METHOD OF MANUFACTURING A VERTICAL MISFET AND A VERTICAL MISFET, AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE
    Publication number: 20110230041
    Abstract: Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.
    Type: Application
    Filed: June 1, 2011
    Publication date: September 22, 2011
    Inventors: Hiraku CHAKIHARA, Kousuke Okuyama, Masahiro Moniwa, Makoto Mizuno, Keiji Okamoto, Mitsuhiro Noguchi, Tadanori Yoshida, Yasuhiko Takahshi, Akio Nishida
  • Semiconductor memory device and a method of manufacturing the same, a method of manufacturing a vertical MISFET and a vertical MISFET, and a method of manufacturing a semiconductor device and a semiconductor device
    Patent number: 7972920
    Abstract: Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.
    Type: Grant
    Filed: February 4, 2010
    Date of Patent: July 5, 2011
    Assignees: Hitachi ULSI Systems Co., Ltd., Renesas Electronics Corp.
    Inventors: Hiraku Chakihara, Kousuke Okuyama, Masahiro Moniwa, Makoto Mizuno, Keiji Okamoto, Mitsuhiro Noguchi, Tadanori Yoshida, Yasuhiko Takahshi, Akio Nishida
  • Semiconductor Memory Device and a Method of Manufacturing the Same, A Method of Manufacturing a Vertical MISFET and a Vertical MISFET, and a Method of Manufacturing a Semiconductor Device and a Semiconductor Device
    Publication number: 20100136778
    Abstract: Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.
    Type: Application
    Filed: February 4, 2010
    Publication date: June 3, 2010
    Inventors: Hiraku Chakihara, Kousuke Okuyama, Masahiro Moniwa, Makoto Mizuno, Keiji Okamoto, Mitsuhiro Noguchi, Tadanori Yoshida, Yasuhiko Takahshi, Akio Nishida
  • Semiconductor memory device and a method of manufacturing the same, a method of manufacturing a vertical MISFET and a vertical MISFET, and a method of manufacturing a semiconductor device and a semiconductor device
    Patent number: 7701020
    Abstract: Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.
    Type: Grant
    Filed: February 2, 2009
    Date of Patent: April 20, 2010
    Assignees: Renesas Technology Corp., Hitachi Ulsi Systems Co., Ltd.
    Inventors: Hiraku Chakihara, Kousuke Okuyama, Masahiro Moniwa, Makoto Mizuno, Keiji Okamoto, Mitsuhiro Noguchi, Tadanori Yoshida, Yasuhiko Takahshi, Akio Nishida
  • SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF MANUFACTURING THE SAME, A METHOD OF MANUFACTURING A VERTICAL MISFET AND A VERTICAL MISFET, AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE
    Publication number: 20090140342
    Abstract: Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.
    Type: Application
    Filed: February 2, 2009
    Publication date: June 4, 2009
    Inventors: Hiraku CHAKIHARA, Kousuke Okuyama, Masahiro Moniwa, Makoto Mizuno, Keiji Okamoto, Mitsuhiro Noguchi, Tadanori Yoshida, Yasuhiko Takahshi, Akio Nishida
  • Semiconductor memory device and a method of manufacturing the same, a method of manufacturing a vertical MISFET and a vertical MISFET, and a method of manufacturing a semiconductor device and a semiconductor device
    Patent number: 7495289
    Abstract: Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.
    Type: Grant
    Filed: May 5, 2006
    Date of Patent: February 24, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Hiraku Chakihara, Kousuke Okuyama, Masahiro Moniwa, Makoto Mizuno, Keiji Okamoto, Mitsuhiro Noguchi, Tadanori Yoshida, Yasuhiko Takahshi, Akio Nishida
  • Semiconductor memory device and a method of manufacturing the same, a method of manufacturing a vertical MISFET and a vertical MISFET, and a method of manufacturing a semiconductor device and a semiconductor device
    Patent number: 7190031
    Abstract: Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.
    Type: Grant
    Filed: July 30, 2003
    Date of Patent: March 13, 2007
    Assignees: Renesas Technology Corp., Hitachi Ulsi Systems Co., Ltd.
    Inventors: Hiraku Chakihara, Kousuke Okuyama, Masahiro Moniwa, Makoto Mizuno, Keiji Okamoto, Mitsuhiro Noguchi, Tadanori Yoshida, Yasuhiko Takahshi, Akio Nishida
  • Semiconductor memory device and method of manufacturing the same, a method of manufacturing a vertical MISFET and a vertical MISFET, and a method of manufacturing a semiconductor device and a semiconductor device
    Patent number: 7161215
    Abstract: Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.
    Type: Grant
    Filed: May 5, 2006
    Date of Patent: January 9, 2007
    Assignees: Renesas Technology Corp., Hitachi Ulsi Systems Co., Ltd.
    Inventors: Hiraku Chakihara, Kousuke Okuyama, Masahiro Moniwa, Makoto Mizuno, Keiji Okamoto, Mitsuhiro Noguchi, Tadanori Yoshida, Yasuhiko Takahshi, Akio Nishida
  • Semiconductor memory device and method of manufacturing the same, a method of manufacturing a vertical MISFET and a vertical MISFET, and a method of manufacturing a semiconductor device and a semiconductor device
    Publication number: 20060208319
    Abstract: Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.
    Type: Application
    Filed: May 5, 2006
    Publication date: September 21, 2006
    Inventors: Hiraku Chakihara, Kousuke Okuyama, Masahiro Moniwa, Makoto Mizuno, Keiji Okamoto, Mitsuhiro Noguchi, Tadanori Yoshida, Yasuhiko Takahshi, Akio Nishida
  • Semiconductor memory device and a method of manufacturing the same, a method of manufacturing a vertical MISFET and a vertical MISFET, and a method of manufacturing a semiconductor device and a semiconductor device
    Publication number: 20060202286
    Abstract: Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.
    Type: Application
    Filed: May 5, 2006
    Publication date: September 14, 2006
    Inventors: Hiraku Chakihara, Kousuke Okuyama, Masahiro Moniwa, Makoto Mizuno, Keiji Okamoto, Mitsuhiro Noguchi, Tadanori Yoshida, Yasuhiko Takahshi, Akio Nishida
  • Semiconductor memory device and a method of manufacturing the same, a method of manufacturing a vertical MISFET and a vertical MISFET, and a method of manufacturing a semiconductor device and a semiconductor device
    Publication number: 20040043550
    Abstract: Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs respectively comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on their corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source, respectively. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are respectively comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.
    Type: Application
    Filed: July 30, 2003
    Publication date: March 4, 2004
    Inventors: Hiraku Chakihara, Kousuke Okuyama, Masahiro Moniwa, Makoto Mizuno, Keiji Okamoto, Mitsuhiro Noguchi, Tadanori Yoshida, Yasuhiko Takahshi, Akio Nishida