Abstract: A switching power supply circuit includes a plurality of switching regulators and a timing adjustment circuit. The plurality of switching regulators converts an input voltage input to an input terminal into a plurality of predetermined constant voltages, and outputs the plurality of predetermined constant voltages from a plurality of output terminals, respectively. The timing adjustment circuit adjusts phases of a plurality of pulse signals generated by the plurality of switching regulators so that the phases of the plurality of pulse signals are different from each other, and outputs the plurality of adjusted pulse signals to respective switch circuits of the plurality of switching regulators.

Abstract: A switching power supply circuit for generating an output voltage at an output node based on an input voltage at an input node includes a reference voltage generating circuit configured to generate a reference voltage such that during an initial start-up period of the reference voltage a voltage rise rate of the reference voltage within a first predetermined period from a start point of the initial start-up period and a voltage rise rate thereof within a second predetermined period immediately preceding an end point of the initial start-up period are smaller than a voltage rise rate thereof in a period between the first predetermined period and the second predetermined period, a coil disposed between the input output nodes, and a switch circuit configured to switch on and off to control current through the coil in response to comparison between the reference voltage and a voltage proportional to the output voltage.

Abstract: A switching power supply circuit for generating an output voltage at an output node based on an input voltage at an input node includes a reference voltage generating circuit configured to generate a reference voltage such that during an initial start-up period of the reference voltage a voltage rise rate of the reference voltage within a first predetermined period from a start point of the initial start-up period and a voltage rise rate thereof within a second predetermined period immediately preceding an end point of the initial start-up period are smaller than a voltage rise rate thereof in a period between the first predetermined period and the second predetermined period, a coil disposed between the input output nodes, and a switch circuit configured to switch on and off to control current through the coil in response to comparison between the reference voltage and a voltage proportional to the output voltage.

Abstract: A switching power supply circuit includes a plurality of switching regulators and a timing adjustment circuit. The plurality of switching regulators converts an input voltage input to an input terminal into a plurality of predetermined constant voltages, and outputs the plurality of predetermined constant voltages from a plurality of output terminals, respectively. The timing adjustment circuit adjusts phases of a plurality of pulse signals generated by the plurality of switching regulators so that the phases of the plurality of pulse signals are different from each other, and outputs the plurality of adjusted pulse signals to respective switch circuits of the plurality of switching regulators.

Abstract: An UART receives asynchronous transmission serial data based on a baud-rate clock from a DTE. An MPU analyzes the data received by the UART. A baud-rate generating portion generates the baud-rate clock to be output to the UART in accordance with instructions from the MPU. A first counter measures the span of the start bit of the first character of an AT command transmitted from the DTE based on instructions from the MPU. A decoder receives a measurement result of the first counter, outputs frequency-dividing data for producing a clock for sampling the first character, and also outputs, when the rate of the start bit is more than a preset value, a flag indicating this matter. A second counter selects, in accordance with whether or not the flag is has been set, the frequency-dividing data from either the decoder or the MPU, and produces the sampling clock.

Abstract: An UART receives asynchronous transmission serial data based on a baud-rate clock from a DTE. An MPU analyzes the data received by the UART. A baud-rate generating portion generates the baud-rate clock to be output to the UART in accordance with instructions from the MPU. A first counter measures the span of the start bit of the first character of an AT command transmitted from the DTE based on instructions from the MPU. A decoder receives a measurement result of the first counter, outputs frequency-dividing data for producing a clock for sampling the first character, and also outputs, when the rate of the start bit is more than a preset value, a flag indicating this matter. A second counter selects, in accordance with whether or not the flag is has been set, the frequency-dividing data from either the decoder or the MPU, and produces the sampling clock.

Abstract: An UART receives asynchronous transmission serial data based on a baud-rate clock from a DTE. An MPU analyzes the data received by the UART. A baud-rate generating portion generates the baud-rate clock to be output to the UART in accordance with instructions from the MPU. A first counter measures the span of the start bit of the first character of an AT command transmitted from the DTE based on instructions from the MPU. A decoder receives a measurement result of the first counter, outputs frequency-dividing data for producing a clock for sampling the first character, and also outputs, when the rate of the start bit is more than a preset value, a flag indicating this matter. A second counter selects, in accordance with whether or not the flag is has been set, the frequency-dividing data from either the decoder or the MPU, and produces the sampling clock.

Abstract: An UART receives asynchronous transmission serial data based on a baud-rate clock from a DTE. An MPU analyzes the data received by the UART. A baud-rate generating portion generates the baud-rate clock to be output to the UART in accordance with instructions from the MPU. A first counter measures the span of the start bit of the first character of an AT command transmitted from the DTE based on instructions from the MPU. A decoder receives a measurement result of the first counter, outputs frequency-dividing data for producing a clock for sampling the first character, and also outputs, when the rate of the start bit is more than a preset value, a flag indicating this matter. A second counter selects, in accordance with whether or not the flag is has been set, the frequency-dividing data from either the decoder or the MPU, and produces the sampling clock.

Abstract: A first counter measures the span of the start bit of a first character of an AT command transmitted from a DTE based on instructions from an MPU. A decoder receives a measurement result of the first counter, outputs frequency-dividing data for producing a clock for sampling the first character, and also outputs, when the rate of the start bit is more than a preset value, a flag indicating this matter. A second counter selects, in accordance with whether or not the flag has been set, the frequency-dividing data from either the decoder or the MPU, and produces the sampling clock. A shift register receives data subsequent to the start bit of the first character based on the sampling clock from the second register, holds the received data, which data is then read by the MPU.

Abstract: A clock signal generator comprises a phase locked loop circuit and a voltage level converting circuit. The phase locked loop circuit is supplied with a control base clock signal and an input clock signal which has a first frequency. The phase locked loop circuit converts the input clock signal to generate a PLL output clock signal which has the second frequency. The input clock signal has one of binary values that has a voltage level which is similar to a reference voltage level of a reference voltage. The voltage level converting circuit is supplied with the PLL output clock signal, the control base clock signal, the reference voltage, and a voltage level control signal. The voltage level converting circuit converts, in response to the control base clock signal, the reference voltage, and the voltage level control signal, the PLL output clock signal to generate an output clock signal which has an output voltage level which is different from the reference voltage level.