Patents by Inventor Yasuhiro Kagawa

Yasuhiro Kagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200144409
    Abstract: A drift layer contains first conductivity type impurities. A well region contains second conductivity type impurities. A source region is provided on the well region and contains the first conductivity type impurities. A well contact region is in contact with the well region, contains the second conductivity type impurities, and has an impurity concentration on the second surface higher than the impurity concentration on the second surface in the well region. A gate electrode is provided on a gate insulating film. A Schottky electrode is in contact with the drift layer. A source ohmic electrode is in contact with the source region. A resistor is in contact with the well contact region and has higher resistance per unit area than the source ohmic electrode.
    Type: Application
    Filed: September 12, 2019
    Publication date: May 7, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kazuya ISHIBASHI, Atsushi NARAZAKI, Yasuhiro KAGAWA, Kensuke TAGUCHI
  • Patent number: 10580889
    Abstract: A first semiconductor layer of a first conductivity type, a first semiconductor region of a second conductivity type provided in an upper layer part thereof, a second semiconductor region of the first conductivity type provided in the upper layer part thereof, a gate trench penetrating through the first and second semiconductor regions in a thickness direction and a bottom surface thereof reaching inside of the first semiconductor layer, a gate insulating film in the gate trench, a gate electrode embedded in the gate trench, a second semiconductor layer of the second conductivity type provided so as to extend, from the bottom surface of the gate trench, a third semiconductor layer of the second conductivity type extending to a position deeper than the bottom surface of the gate trench, and a fourth semiconductor layer of the first conductivity type interposed between the second semiconductor layer and the third semiconductor layer in the position deeper than the bottom surface of the gate trench.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: March 3, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yasuhiro Kagawa
  • Patent number: 10510843
    Abstract: An insulated gate silicon carbide semiconductor device includes: a drift layer of a first conductivity type on a silicon carbide substrate of 4H type with a {0001} plane having an off-angle of more than 0° as a main surface; a first base region; a source region; a trench; a gate insulating film; a protective diffusion layer; and a second base region. The trench sidewall surface in contact with the second base region is a surface having a trench off-angle of more than 0° in a <0001> direction with respect to a plane parallel to the <0001> direction. The insulated gate silicon carbide semiconductor device can relieve an electric field of a gate insulating film and suppress an increase in on-resistance and provide a method for manufacturing the same.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: December 17, 2019
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yasuhiro Kagawa, Rina Tanaka, Yutaka Fukui, Naruhisa Miura, Yuji Abe, Masayuki Imaizumi
  • Publication number: 20190348524
    Abstract: A drift layer has a first conductivity type and is provided on a silicon carbide substrate. A well region has a second conductivity type and is provided on the drift layer. A source region has the first conductivity type and is provided on the well region. A gate trench has an inner surface with a bottom located at a deeper position than the well region and a lateral part continuous with the bottom. An electric field relaxation region has the second conductivity type and has at least a part located below the bottom of the gate trench. A surge relaxation region has the first conductivity type, contacts at least a part of the bottom of the gate trench, and is separated from the drift layer by the electric field relaxation region.
    Type: Application
    Filed: April 1, 2019
    Publication date: November 14, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yuji EBIIKE, Yasuhiro KAGAWA
  • Patent number: 10453951
    Abstract: A trench-gate semiconductor device including an outside trench, increases reliability of an insulating film at a corner of an open end of the outside trench. The semiconductor device includes: a gate trench reaching an inner part of an n-type drift layer in a cell region; an outside trench outside the cell region; a gate electrode formed inside the gate trench through a gate insulating film; a gate line formed inside the outside trench through an insulating film; and a gate line leading portion formed through the insulating film to cover a corner of an open end of the outside trench closer to the cell region, and electrically connecting the gate electrode to the gate line, and the surface layer of the drift layer in contact with the corner has a second impurity region of p-type that is a part of the well region.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: October 22, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yutaka Fukui, Yasuhiro Kagawa, Kensuke Taguchi, Nobuo Fujiwara, Katsutoshi Sugawara, Rina Tanaka
  • Patent number: 10431658
    Abstract: A gate trench and a protective trench are provided on a top surface of the silicon carbide semiconductor layer of a first conductivity type. A protective diffusion layer of a second conductivity type is provided at a position deeper than the gate electrode in the silicon carbide semiconductor layer. An inter-layer insulating film covers a surface of the gate electrode and includes a cell opening. A source electrode is electrically connected to the source region via the cell opening and electrically connected to the protective diffusion layer via the protective trench. A plated film is provided on the source electrode. A concave part is provided on a top surface of the source electrode above the protective trench. A depth in a vertical direction of the concave part is equal to or less than half of a width in a horizontal direction of the concave part.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: October 1, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yasuhiro Kagawa, Atsushi Narazaki, Yutaka Fukui, Katsutoshi Sugawara
  • Publication number: 20190259872
    Abstract: A first semiconductor layer of a first conductivity type, a first semiconductor region of a second conductivity type provided in an upper layer part thereof, a second semiconductor region of the first conductivity type provided in the upper layer part thereof, a gate trench penetrating through the first and second semiconductor regions in a thickness direction and a bottom surface thereof reaching inside of the first semiconductor layer, a gate insulating film in the gate trench, a gate electrode embedded in the gate trench, a second semiconductor layer of the second conductivity type provided so as to extend, from the bottom surface of the gate trench, a third semiconductor layer of the second conductivity type extending to a position deeper than the bottom surface of the gate trench, and a fourth semiconductor layer of the first conductivity type interposed between the second semiconductor layer and the third semiconductor layer in the position deeper than the bottom surface of the gate trench.
    Type: Application
    Filed: December 27, 2018
    Publication date: August 22, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventor: Yasuhiro KAGAWA
  • Patent number: 10351811
    Abstract: A cell culture container characterized by being equipped with a container main body and a flat plate attached onto one surface of the container main body, wherein the container main body is equipped with an inflow port through which a liquid can flow into the container main body, a passage through which the liquid flowing into the container main body from the inflow port can pass, and an outflow port through which the liquid passing through the passage can flow out from the container main body, and wherein, on the bottom surface of the passage, multiple cell-seeding areas in which cells passing through the passage can be seeded are arranged side by side along the passage.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: July 16, 2019
    Assignee: SINFONIA TECHNOLOGY CO., LTD.
    Inventors: Tomoaki Kurakazu, Yasuhiro Oshima, Yoshio Kimura, Kenichi Kagawa, Shinichi Gomi, Shigenori Ozaki
  • Patent number: 10347724
    Abstract: A gate insulating film covers a trench penetrating through a source region and a body region and reaching a drift layer in each of a first cell region and a second cell region. The gate electrode is provided in the trench. A high-concentration layer of the first conductivity type is provided between the drift layer and the body region in the first cell region and has a second impurity concentration higher than the first impurity concentration. A current restriction layer is provided between the drift layer and the body region in the second cell region and has the first conductivity type and a third impurity concentration higher than the first impurity concentration and lower than the second impurity concentration.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: July 9, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Rina Tanaka, Katsutoshi Sugawara, Yasuhiro Kagawa, Naruhisa Miura
  • Patent number: 10312233
    Abstract: A semiconductor device includes a base region of second conductivity type formed on a drift layer of first conductivity type, a source region of first conductivity type located in the base region, a trench passing through the base region and the source region and dividing cell regions in plan view, a protective diffusion layer of second conductivity type disposed on a bottom of the trench, a gate electrode embedded in the trench with a gate insulating film therebetween, a source electrode electrically connected to the source region, and a protective contact region disposed at each of positions of three or more cell regions and connecting the protective diffusion layer and the source electrode to each other. The protective contact regions are disposed such that a triangle whose vertices are centers of three protective contact regions located closest to one another is an acute triangle.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: June 4, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Katsutoshi Sugawara, Yasuhiro Kagawa, Rina Tanaka, Yutaka Fukui
  • Publication number: 20190164127
    Abstract: A delivery system includes a vehicle and a management server configured to communicate with the vehicle. The vehicle is configured to perform unmanned driving and used to deliver a baggage to a designated delivery destination. When an arrival time of a user, who moves to the delivery destination without riding on the vehicle, to the delivery destination is set, the management server is configured to transmit, to the vehicle, an instruction for moving the vehicle in accordance with a delivery route searched to allow the vehicle to reach the delivery destination at the set arrival time. The vehicle moves to the delivery destination in accordance with the instruction.
    Type: Application
    Filed: November 6, 2018
    Publication date: May 30, 2019
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Naomi KATAOKA, Toshiaki NIWA, Yasuhiro BABA, Katsuhiko YOUROU, Kazuyuki KAGAWA
  • Publication number: 20190138023
    Abstract: Each vehicle is configured to perform automated driving and includes a camera and an ECU. The camera is configured to capture an image of a situation outside the vehicle. The ECU receives an image capture request including an image capture location through a communication module. The ECU performs control for causing the vehicle to move to the image capture location and capturing an image of a situation outside the vehicle by the camera in accordance with the image capture request.
    Type: Application
    Filed: October 9, 2018
    Publication date: May 9, 2019
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Toshiaki NIWA, Naomi KATAOKA, Yasuhiro BABA, Katsuhiko YOUROU, Kazuyuki KAGAWA
  • Patent number: 10229969
    Abstract: A protective diffusion region includes a first protective diffusion region at a location closest to a termination region, and a second protective diffusion region located away from the first protective diffusion region with a first space therebetween. A second space that is a distance between a termination diffusion region and the first protective diffusion region is greater than the first space. A current diffusion layer of a first conductivity type includes a first current diffusion layer located between the first protective diffusion region and the second protective diffusion region and having a higher impurity concentration than a drift layer, and a second current diffusion layer located between the first protective diffusion region and the termination diffusion region. The second current diffusion layer includes a region having a lower impurity concentration than the current diffusion layer.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: March 12, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yasuhiro Kagawa, Rina Tanaka, Yutaka Fukui, Katsutoshi Sugawara
  • Patent number: 10199457
    Abstract: A silicon carbide semiconductor device includes a silicon carbide drift layer formed on an upper surface of a silicon carbide semiconductor substrate having an off angle, a body region, a source region, a plurality of trenches, a gate insulating film, a gate electrode, a source electrode, a drain electrode, and a depletion suppressing layer. The depletion suppressing layer is positioned to be sandwiched between the plurality of trenches in a plan view, and in a direction with the off angle of the silicon carbide semiconductor substrate, a distance between the depletion suppressing layer and one of the trenches adjacent to the depletion suppressing layer is different from another distance between the depletion suppressing layer and the other one of the trenches adjacent to the depletion suppressing layer.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: February 5, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Rina Tanaka, Yutaka Fukui, Katsutoshi Sugawara, Takeharu Kuroiwa, Yasuhiro Kagawa
  • Publication number: 20190013385
    Abstract: A gate trench and a protective trench are provided on a top surface of the silicon carbide semiconductor layer of a first conductivity type. A protective diffusion layer of a second conductivity type is provided at a position deeper than the gate electrode in the silicon carbide semiconductor layer. An inter-layer insulating film covers a surface of the gate electrode and includes a cell opening. A source electrode is electrically connected to the source region via the cell opening and electrically connected to the protective diffusion layer via the protective trench. A plated film is provided on the source electrode. A concave part is provided on a top surface of the source electrode above the protective trench. A depth in a vertical direction of the concave part is equal to or less than half of a width in a horizontal direction of the concave part.
    Type: Application
    Filed: February 22, 2018
    Publication date: January 10, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yasuhiro KAGAWA, Atsushi NARAZAKI, Yutaka FUKUI, Katsutoshi SUGAWARA
  • Patent number: 10157986
    Abstract: A drift layer of a first conductivity type is made of silicon carbide. A body region of a second conductivity type is provided on the drift layer. A source region of the first conductivity type is provided on the body region. A source electrode is connected to the source region. A gate insulating film is provided on side and bottom surfaces of a trench which penetrates the body region and the source region. A gate electrode is provided in the trench with the gate insulating film interposed therebetween. A trench-bottom-surface protective layer of the second conductivity type provided below the bottom surface of the trench in the drift layer is electrically connected to the source electrode. The trench-bottom-surface protective layer has a high-concentration protective layer, and a first low-concentration protective layer provided below the high-concentration protective layer and having an impurity concentration lower than that of the high-concentration protective layer.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: December 18, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Rina Tanaka, Yasuhiro Kagawa, Katsutoshi Sugawara, Naruhisa Miura
  • Publication number: 20180358431
    Abstract: A protective diffusion region includes a first protective diffusion region at a location closest to a termination region, and a second protective diffusion region located away from the first protective diffusion region with a first space therebetween. A second space that is a distance between a termination diffusion region and the first protective diffusion region is greater than the first space. A current diffusion layer of a first conductivity type includes a first current diffusion layer located between the first protective diffusion region and the second protective diffusion region and having a higher impurity concentration than a drift layer, and a second current diffusion layer located between the first protective diffusion region and the termination diffusion region. The second current diffusion layer includes a region having a lower impurity concentration than the current diffusion layer.
    Type: Application
    Filed: May 16, 2016
    Publication date: December 13, 2018
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yasuhiro KAGAWA, Rina TANAKA, Yutaka FUKUI, Katsutoshi SUGAWARA
  • Publication number: 20180358429
    Abstract: A silicon carbide semiconductor device includes a silicon carbide drift layer formed on an upper surface of a silicon carbide semiconductor substrate having an off angle, a body region, a source region, a plurality of trenches, a gate insulating film, a gate electrode, a source electrode, a drain electrode, and a depletion suppressing layer. The depletion suppressing layer is positioned to be sandwiched between the plurality of trenches in a plan view, and in a direction with the off angle of the silicon carbide semiconductor substrate, a distance between the depletion suppressing layer and one of the trenches adjacent to the depletion suppressing layer is different from another distance between the depletion suppressing layer and the other one of the trenches adjacent to the depletion suppressing layer.
    Type: Application
    Filed: September 29, 2016
    Publication date: December 13, 2018
    Applicant: Mitsubishi Electric Corporation
    Inventors: Rina TANAKA, Yutaka FUKUI, Katsutoshi SUGAWARA, Takeharu KUROIWA, Yasuhiro KAGAWA
  • Publication number: 20180315819
    Abstract: A gate insulating film covers a trench penetrating through a source region and a body region and reaching a drift layer in each of a first cell region and a second cell region. The gate electrode is provided in the trench. A high-concentration layer of the first conductivity type is provided between the drift layer and the body region in the first cell region and has a second impurity concentration higher than the first impurity concentration. A current restriction layer is provided between the drift layer and the body region in the second cell region and has the first conductivity type and a third impurity concentration higher than the first impurity concentration and lower than the second impurity concentration.
    Type: Application
    Filed: December 7, 2015
    Publication date: November 1, 2018
    Applicant: Mitsubishi Electric Corporation
    Inventors: Rina TANAKA, Katsutoshi SUGAWARA, Yasuhiro KAGAWA, Naruhisa MIURA
  • Patent number: 9985093
    Abstract: There is provided a trench-gate type semiconductor device that can prevent breakdown of a gate insulating film caused by a displacement current flowing into a protective diffusion layer at a portion of a trench underlying a gate electrode at a turn-off time and simultaneously improves a current density by narrowing a cell pitch. The semiconductor device has a gate electrode 7 embedded into a trench 5 penetrating a base region 3. The gate electrode 7 is disposed into a lattice shape in a planar view, and a protective diffusion layer 13 is formed in a drift layer 2a at the portion underlying thereof. At least one of blocks divided by the gate electrode 7 is a protective contact region 20 on which the trench 5 is entirely formed. A protective contact 21 for connecting the protective diffusion layer 13 at a bottom portion of the trench 5 and a source electrode 9 is disposed on the protective contact region 20.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: May 29, 2018
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yasuhiro Kagawa, Akihiko Furukawa, Shiro Hino, Hiroshi Watanabe, Masayuki Imaizumi