Patents by Inventor Yasuhiro Nishisaka

Yasuhiro Nishisaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10535468
    Abstract: A method for manufacturing a multilayer ceramic capacitor includes preparing a green multilayer body including a stack of dielectric sheets printed with inner electrodes, coating the green multilayer body with a conductive paste that is connected to the inner electrodes, and firing the conductive paste and the green multilayer body at the same time, wherein a rate of temperature increase from about 800° C. to about 1,100° C. during the firing is about 15° C. per minute or more.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: January 14, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Takehisa Sasabayashi, Yasuhiro Nishisaka, Satoshi Matsuno, Yoko Okabe
  • Patent number: 10529486
    Abstract: A conductive paste for an external electrode that includes a conductive metal powder; a glass frit having an average particle diameter D50 of not more than 0.8 ?m and having a flat shape with an average flatness of 1.5 to 5.5; and a binder resin. A method of manufacturing an electronic component includes preparing an electronic component element; applying the conductive paste for an external electrode onto an outer surface of the electronic component element; and baking the applied conductive paste to form an external electrode.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: January 7, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Yasuhiro Nishisaka
  • Patent number: 10510496
    Abstract: A multilayer ceramic capacitor includes a multilayer body that includes ceramic layers and inner conductor layers arranged in a stacking direction and that includes a first surface in which the inner conductor layers are exposed, and an outer electrode on the first surface of the multilayer body. The inner conductor layers contain Ni. The outer electrode includes a base layer that directly covers at least a portion of the first surface and is connected to the inner conductor layers. The base layer contains a metal and glass and includes a Ni diffusion portion connected to the inner conductor layers, the Ni diffusion portion containing Ni. A ratio of a diffusion depth of the Ni diffusion portion to a thickness of the base layer is smaller on two of the inner conductor layers that are located outermost than on other inner conductor layers.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: December 17, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Masato Kimura, Yasuhiro Nishisaka
  • Patent number: 10504651
    Abstract: A multilayer ceramic capacitor includes a laminate in which dielectric layers and internal electrodes are alternately stacked, and a pair of external electrodes provided on the corresponding surfaces of the laminate. The laminate includes first and second principal surfaces facing each other in its thickness direction, first and second end surfaces facing each other in its lengthwise direction, and first and second side surfaces facing each other in its width direction. The external electrodes each include a metal layer covering the internal electrodes extended to the corresponding one of the end surfaces, a baked layer including glass and metal covering the metal layer, and a plated film covering the baked layer.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: December 10, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yasuhiro Nishisaka, Akito Mori
  • Patent number: 10483041
    Abstract: A first outer electrode and first inner electrodes are supplied with an anode potential and a second outer electrode and second inner electrodes are supplied with a cathode potential when a monolithic ceramic capacitor is mounted and in use. The first outer electrode supplied with the anode potential has a thickness that is greater than a thickness of the second outer electrode supplied with the cathode potential.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: November 19, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yoshito Saito, Satoshi Matsuno, Shinji Otani, Tomochika Miyazaki, Yasuhiro Nishisaka
  • Patent number: 10483039
    Abstract: A conductive paste for an external electrode that includes a conductive metal powder; a glass frit having an average particle diameter D50 of not more than 0.8 ?m and having a flat shape with an average flatness of 1.5 to 5.5; and a binder resin. A method of manufacturing an electronic component includes preparing an electronic component element; applying the conductive paste for an external electrode onto an outer surface of the electronic component element; and baking the applied conductive paste to form an external electrode.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: November 19, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Yasuhiro Nishisaka
  • Patent number: 10418191
    Abstract: An outer electrode includes sintered layers each containing a sintered metal, an electrically insulating glass layer, and metal layers each containing at least one of Sn and Cu. Each sintered layer covers a respective end surface of a body and extends from the end surface to at least one main surface of the body. The glass layer is directly provided on the sintered layers located on the end surfaces of the body, extends in a direction perpendicular or substantially perpendicular to side surfaces of the body, and defines a portion of a surface of the outer electrode. Each metal layer covers a portion of one of the sintered layers other than a portion of the corresponding sintered layer that is covered with the glass layer, and defines another portion of the surface of the outer electrode.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: September 17, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yasuhiro Nishisaka, Tomoe Tanaka
  • Patent number: 10366838
    Abstract: A laminated ceramic electronic component that includes a laminate having a plurality of dielectric layers and a plurality of internal electrode layers laminated together. External electrodes having underlying electrode layers and plating layers are formed on both end surfaces of the laminate. When a cross-section including the underlying electrode layers is observed, the underlying electrode layers contain a plurality of Cu crystals and glass, and an average value of lengths of demarcation lines of the Cu crystals having different crystal orientations is 3 ?m or less.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: July 30, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yasuhiro Nishisaka, Masato Kimura
  • Publication number: 20190051467
    Abstract: A multilayer ceramic capacitor includes a multilayer body that includes ceramic layers and inner conductor layers arranged in a stacking direction and that includes a first surface in which the inner conductor layers are exposed, and an outer electrode on the first surface of the multilayer body. The inner conductor layers contain Ni. The outer electrode includes a base layer that directly covers at least a portion of the first surface and is connected to the inner conductor layers. The base layer contains a metal and glass and includes a Ni diffusion portion connected to the inner conductor layers, the Ni diffusion portion containing Ni. A ratio of a diffusion depth of the Ni diffusion portion to a thickness of the base layer is smaller on two of the inner conductor layers that are located outermost than on other inner conductor layers.
    Type: Application
    Filed: October 12, 2018
    Publication date: February 14, 2019
    Inventors: Masato KIMURA, Yasuhiro NISHISAKA
  • Publication number: 20180342355
    Abstract: A laminated ceramic electronic component that includes a laminate having a plurality of dielectric layers and a plurality of internal electrode layers laminated together. External electrodes having underlying electrode layers and plating layers are formed on both end surfaces of the laminate. When a cross-section including the underlying electrode layers is observed, the underlying electrode layers contain a plurality of Cu crystals and glass, and an average value of lengths of demarcation lines of the Cu crystals having different crystal orientations is 3 ?m or less.
    Type: Application
    Filed: July 31, 2018
    Publication date: November 29, 2018
    Inventors: Yasuhiro Nishisaka, Masato Kimura
  • Patent number: 10134533
    Abstract: A multilayer ceramic capacitor includes a multilayer body that includes ceramic layers and inner conductor layers arranged in a stacking direction and that includes a first surface in which the inner conductor layers are exposed, and an outer electrode on the first surface of the multilayer body. The inner conductor layers contain Ni. The outer electrode includes a base layer that directly covers at least a portion of the first surface and is connected to the inner conductor layers. The base layer contains a metal and glass and includes a Ni diffusion portion connected to the inner conductor layers, the Ni diffusion portion containing Ni. A ratio of a diffusion depth of the Ni diffusion portion to a thickness of the base layer is smaller on two of the inner conductor layers that are located outermost than on other inner conductor layers.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: November 20, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Masato Kimura, Yasuhiro Nishisaka
  • Publication number: 20180301280
    Abstract: A conductive paste for an external electrode that includes a conductive metal powder; a glass frit having an average particle diameter D50 of not more than 0.8 ?m and having a flat shape with an average flatness of 1.5 to 5.5; and a binder resin. A method of manufacturing an electronic component includes preparing an electronic component element; applying the conductive paste for an external electrode onto an outer surface of the electronic component element; and baking the applied conductive paste to form an external electrode.
    Type: Application
    Filed: April 11, 2018
    Publication date: October 18, 2018
    Inventor: YASUHIRO NISHISAKA
  • Patent number: 10090108
    Abstract: A multilayer ceramic capacitor having an external electrode with a glass phase, where an occupation rate of the glass phase is 30% to 60% on an area ratio, and a maximum length c of the glass phase is 5 ?m or less.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: October 2, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Tetsuya Kisumi, Toshiki Nagamoto, Yasuhiro Nishisaka, Yoko Okabe
  • Patent number: 10068710
    Abstract: A laminated ceramic electronic component that includes a laminate having a plurality of dielectric layers and a plurality of internal electrode layers laminated together. External electrodes having underlying electrode layers and plating layers are formed on both end surfaces of the laminate. When a cross-section including the underlying electrode layers is observed, the underlying electrode layers contain a plurality of Cu crystals and glass, and an average value of lengths of demarcation lines of the Cu crystals having different crystal orientations is 3 ?m or less.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: September 4, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yasuhiro Nishisaka, Masato Kimura
  • Patent number: 10014110
    Abstract: A multilayer ceramic capacitor includes an external electrode that is unlikely to be peeled. First and second external electrodes each include base layers provided over a ceramic body and including a metal and glass, and Cu plated layers provided over the base layers. The multilayer ceramic capacitor includes a reactive layer. The reactive layer contains about 5 atomic % to about 15 atomic % of Ti, about 5 atomic % to about 15 atomic % of Si, and about 2 atomic % to about 10 atomic % of V.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: July 3, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasuhiro Nishisaka, Takehisa Sasabayashi, Satoshi Muramatsu
  • Patent number: 10008327
    Abstract: A multilayer ceramic capacitor that includes a laminate which has a plurality of dielectric layers and a plurality of internal electrode layers respectively laminated. The dielectric layers are a perovskite type structure containing Ba, Sr, Zr, Ti and Hf, and optionally Ca, and further include V, wherein (number of moles of Sr)/(number of moles of Ba+number of moles of Ca+number of moles of Sr) is 0.6 to 0.95, (number of moles of Zr)/(number of moles of Zr+number of moles of Ti+number of moles of Hf) is 0.9 to 0.98, thicknesses of the dielectric layers are 1 ?m or less, and an average particle size of dielectric particles constituting the dielectric layers is 0.8 ?m or less.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: June 26, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Shinya Isota, Tatsuya Izumi, Tomotaka Hirata, Yasuhiro Nishisaka
  • Patent number: 9978518
    Abstract: In a multilayer ceramic capacitor, each outer electrode includes a first outer electrode layer that contains Ni and that is disposed on each main surface of a multilayer body and a second outer electrode layer that contains a glass component and Cu and that covers one end portion of the first outer electrode layer which is closer to an end surface of the multilayer body, the first and second outer electrode layers are joined together in a region including an edge shared by the main surface and the end surface, the other end portion of the first outer electrode layer is exposed from the second outer electrode layer, and Ni of the first outer electrode layer is diffused in the second outer electrode layer and is dissolved in Cu of the second outer electrode layer to define a solid solution in the region including the edge.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: May 22, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Yasuhiro Nishisaka
  • Patent number: 9959973
    Abstract: A multilayer ceramic capacitor that includes a layered body in which dielectric layers and internal electrode layers are layered alternately, an external electrode on a surface of the layered body and a plating layer on a surface of the external electrode. The external electrode contains Cu, and a protective layer containing Cu2O is provided at a joining portion between the external electrode and the plating layer. When heat is applied to the layered body after the external electrode is removed, a ratio of an arithmetic mean value Xa of a quantity of hydrogen generated per unit temperature in a range higher than or equal to 350° C. with respect to an arithmetic mean value Y of a quantity of hydrogen generated per unit temperature in a range higher than or equal to 230° C. and lower than or equal to 250° C. (Xa/Y) is less than or equal to 0.66.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: May 1, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yoshito Saito, Yasuhiro Nishisaka, Makoto Ogawa, Akihiro Tsuru
  • Publication number: 20180108483
    Abstract: A method for manufacturing a multilayer ceramic capacitor includes preparing a green multilayer body including a stack of dielectric sheets printed with inner electrodes, coating the green multilayer body with a conductive paste that is connected to the inner electrodes, and firing the conductive paste and the green multilayer body at the same time, wherein a rate of temperature increase from about 800° C. to about 1,100° C. during the firing is about 15° C. per minute or more.
    Type: Application
    Filed: October 16, 2017
    Publication date: April 19, 2018
    Inventors: Takehisa SASABAYASHI, Yasuhiro NISHISAKA, Satoshi MATSUNO, Yoko OKABE
  • Publication number: 20180096791
    Abstract: A multilayer ceramic capacitor includes a laminate in which dielectric layers and internal electrodes are alternately stacked, and a pair of external electrodes provided on the corresponding surfaces of the laminate. The laminate includes first and second principal surfaces facing each other in its thickness direction, first and second end surfaces facing each other in its lengthwise direction, and first and second side surfaces facing each other in its width direction. The external electrodes each include a metal layer covering the internal electrodes extended to the corresponding one of the end surfaces, a baked layer including glass and metal covering the metal layer, and a plated film covering the baked layer.
    Type: Application
    Filed: October 3, 2017
    Publication date: April 5, 2018
    Inventors: Yasuhiro NISHISAKA, Akito MORI