Patents by Inventor Yasuhiro Okamoto
Yasuhiro Okamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200367725Abstract: An external mechanism for endoscope includes a wheel engaged with a second bending operation up and down knob of a second bending operation apparatus provided in an operation portion of an endoscope, a motor configured to generate driving force for rotating the wheel, an operation switch for outputting a driving control signal to the motor, a container case containing the wheel and the motor, a case attachment and detachment fixation member with which the container case can be attached to and detached from the operation portion, a switch case attached to the container case and configured to be able to turn between a first position covering a part of the operation portion and a second position away from the first position, and a dummy switch provided in the switch case and configured to operate a remote switch arranged in the operation portion in the first position via the switch case.Type: ApplicationFiled: June 15, 2020Publication date: November 26, 2020Applicant: OLYMPUS CORPORATIONInventor: Yasuhiro OKAMOTO
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Patent number: 10736493Abstract: An insertion device includes a shape-variable tube elastically returning while the shape-variable tube bends at a tube bending radius of a tube radius boundary value or more, and a shaft rotating around a shaft axis inside the shape-variable tube so that the shaft transmits a driving force to drive a motion section from a first extending direction toward a second extending direction. The shaft elastically returns while the shaft bends at a shaft bending radius of a shaft radius boundary value or more, and rotates without being deformed while the elastic return is impossible when the shape-variable tube bends in an elastically returnable range.Type: GrantFiled: February 5, 2016Date of Patent: August 11, 2020Assignee: OLYMPUS CORPORATIONInventor: Yasuhiro Okamoto
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Publication number: 20200161480Abstract: In a Schottky barrier diode region, a Schottky barrier diode is formed between an n-type drift layer and a metal layer, and in a body diode region, a p-type semiconductor region, a p-type semiconductor region, and a p-type semiconductor region are formed in order from a main surface side in the drift layer, and a body diode is formed between the p-type semiconductor region and the drift layer. An impurity concentration of the p-type semiconductor region is decreased lower than the impurity concentration of the p-type semiconductor regions, thereby increasing the reflux current flowing through the Schottky barrier diode and preventing the reflux current from flowing through the body diode.Type: ApplicationFiled: October 10, 2019Publication date: May 21, 2020Inventors: Yasuhiro OKAMOTO, Nobuo MACHIDA, Kenichi HISADA
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Publication number: 20200161445Abstract: An n-type epitaxial layer is formed on an n-type semiconductor substrate made of silicon carbide. p-type body regions are formed in the epitaxial layer, and n-type source region is formed in the body region. On the body region between the source region and the epitaxial layer, a gate electrode is formed via a gate dielectric film, and an interlayer insulating film having an opening is formed so as to cover the gate electrode. A source electrode electrically connected to the source region and the body regions is formed in the opening. A recombination layer is formed between the body region and a basal plane dislocation is a layer having point defect density higher than that of the epitaxial layer located directly under the recombination layer or having a metal added to the epitaxial layer.Type: ApplicationFiled: October 9, 2019Publication date: May 21, 2020Inventors: Hironobu MIYAMOTO, Yasuhiro OKAMOTO, Kenichi HISADA, Koichi ARAI, Nobuo MACHIDA
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Patent number: 10566183Abstract: Characteristics of a semiconductor device are improved. A method of manufacturing a semiconductor device of the invention includes a step of forming a gate insulating film over a nitride semiconductor layer. The step includes steps of forming a crystalline Al2O3 film on the nitride semiconductor layer, forming a SiO2 film on the Al2O3 film, and forming an amorphous Al2O3 film on the SiO2 film. The step further includes steps of performing heat treatment on the amorphous Al2O3 to crystallize the amorphous Al2O3, thereby forming a crystalline Al2O3 film, and forming a SiO2 film on the crystalline Al2O3 film. In this way, since a film stack, which is formed by alternately stacking the crystalline Al2O3 films and the SiO2 films from a bottom side, is used as the gate insulating film, threshold voltage can be cumulatively increased.Type: GrantFiled: August 2, 2018Date of Patent: February 18, 2020Assignee: Renesas Electronics CorporationInventors: Yasuhiro Okamoto, Takashi Ide
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Patent number: 10537229Abstract: An introduction device includes an operation main body, a bending section capable of bending in a first direction and a second direction, a first rotary body configured to be operated at a time of bending the bending section in the first direction, and a second rotary body configured to be operated at a time of bending the bending section in the second direction, the second rotary body being configured such that a part of an outer edge is located on an extension plane which is defined by extending the first surface, or the part of the outer edge is located more on the distal-end direction side of the first shaft portion than the extension plane.Type: GrantFiled: February 12, 2016Date of Patent: January 21, 2020Assignee: OLYMPUS CORPORATIONInventor: Yasuhiro Okamoto
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Patent number: 10541321Abstract: In a manufacturing method of a semiconductor device according to the present invention, a buffer layer including a first nitride semiconductor layer, a channel layer including a second nitride semiconductor layer, and a barrier layer including a third nitride semiconductor layer are sequentially laminated, and a fourth nitride semiconductor layer is further laminated thereover. Then, a laminate of a gate insulating film and a gate electrode is formed over a first region of the fourth nitride semiconductor layer, and a silicon nitride film is formed over the fourth nitride semiconductor layer and the laminate. By bringing the fourth nitride semiconductor layers on both sides of the gate electrode into contact with the silicon nitride film in this way, the function of suppressing 2DEG can be lowered, and the 2DEG that has been eliminated after the formation of the fourth nitride semiconductor layer can be restored.Type: GrantFiled: July 5, 2018Date of Patent: January 21, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Yasuhiro Okamoto
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Patent number: 10517463Abstract: An endoscope operation mechanism includes: a dial operating an endoscope function; a detection sensor that has a sensor rotation shaft to which rotation of a dial rotation shaft of the dial is transmitted and detects the rotation amount, and that outputs an electrical signal in accordance with the detected rotation amount to a control portion performing driving control of a driving source of the endoscope function; an initial position reversion mechanism applying a rotational force to the dial rotation shaft in an opposite direction to the direction in which the dial rotation shaft is rotated, to thereby cause the rotational position of the dial to return to an initial position; and a switching mechanism switchable between a first state in which a rotational force from the initial position reversion mechanism is applied to the dial rotation shaft, and a second state in which the rotational force is not applied.Type: GrantFiled: March 2, 2017Date of Patent: December 31, 2019Assignee: OLYMPUS CORPORATIONInventor: Yasuhiro Okamoto
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Patent number: 10461159Abstract: Characteristics of a semiconductor device using a nitride semiconductor are improved. A semiconductor device of the present invention includes a buffer layer, a channel layer, a barrier layer, a mesa-type 2DEG dissolving layer, a source electrode, a drain electrode, a gate insulating film formed on the mesa-type 2DEG dissolving layer, and an overlying gate electrode. The gate insulating film of the semiconductor device includes a sputtered film formed on the mesa-type 2DEG dissolving layer and a CVD film formed on the sputtered film. The sputtered film is formed in a non-oxidizing atmosphere by a sputtering process using a target including an insulator. This makes it possible to reduce positive charge amount at a MOS interface and in gate insulating film and increase a threshold voltage, and thus improve normally-off characteristics.Type: GrantFiled: April 30, 2018Date of Patent: October 29, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hironobu Miyamoto, Tatsuo Nakayawa, Yasuhiro Okamoto, Atsushi Tsuboi
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Patent number: 10413163Abstract: An introduction device includes, a grip portion which has a first wall portion, and a second wall portion, a curving portion which is configured to curve in a first surface and in a second surface that intersects at right angles with the first surface, a first dial portion which is rotatably provided in the first wall portion and which curves the curving portion in the first surface in accordance with a rotation amount, and a dial unit includes a shaft rotatably provided on the second wall portion, and a second dial portion which is fixed to the shaft and which curves the curving portion in the second surface in accordance with a rotation amount, the shaft being oblique to the longitudinal axis when seen from the side of the second wall portion.Type: GrantFiled: November 13, 2015Date of Patent: September 17, 2019Assignee: OLYMPUS CORPORATIONInventor: Yasuhiro Okamoto
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Patent number: 10410868Abstract: A semiconductor device includes a first nitride semiconductor layer formed over a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer and having a band gap wider than a band gap of the first nitride semiconductor layer, a trench penetrating through the second nitride semiconductor layer and reaching an inside of the first nitride semiconductor layer, a gate electrode placed in the trench over a gate insulating film, and a first electrode and a second electrode formed over the second nitride semiconductor layer on both sides of the gate electrode, respectively.Type: GrantFiled: January 29, 2018Date of Patent: September 10, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Takashi Inoue, Tatsuo Nakayama, Yasuhiro Okamoto, Hiroshi Kawaguchi, Toshiyuki Takewaki, Nobuhiro Nagura, Takayuki Nagai, Yoshinao Miura, Hironobu Miyamoto
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Patent number: 10396190Abstract: Characteristics of a semiconductor device are improved. A semiconductor device includes a sequential stack of a buffer layer, a channel layer, and a barrier layer, and includes a mesa part including a fourth nitride semiconductor layer formed over the stack, and a side part formed on both sides of the mesa part and including a thin film part of the fourth nitride semiconductor layer. Generation of 2DEG is suppressed below the mesa part while being unsuppressed below the side part. In this way, the side part that disables the 2DEG suppression effect is provided on an end portion of the mesa part, thereby a distance from an end portion of the side part to the gate electrode is increased, making it possible to suppress leakage caused by a current path passing through an undesired channel formed between a gate insulating film and the mesa part.Type: GrantFiled: May 22, 2018Date of Patent: August 27, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Takehiro Ueda, Yasuhiro Okamoto
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Publication number: 20190237577Abstract: A drift layer is formed over a semiconductor substrate which is an SiC substrate. The drift layer includes first to third n-type semiconductor layers and a p-type impurity region. Herein, an impurity concentration of the second n-type semiconductor layer is higher than an impurity concentration of the first n-type semiconductor layer and an impurity concentration of the third n-type semiconductor layer. Also, in plan view, the second semiconductor layer located between the p-type impurity regions adjacent to each other overlaps with at least a part of a gate electrode formed in a trench.Type: ApplicationFiled: December 18, 2018Publication date: August 1, 2019Inventors: Yasuhiro OKAMOTO, Nobuo MACHIDA, Koichi ARAI, Kenichi HISADA, Yasunori YAMASHITA, Satoshi EGUCHI, Hironobu MIYAMOTO, Atsushi SAKAI, Katsumi EIKYU
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Patent number: 10363888Abstract: A wire harness to be installed in a vehicle includes an electric wire and a protective tube that protects the electric wire. The electric wire is provided at the lower part of a vehicle body of the vehicle and the protective tube covers the electric wire and includes ferromagnetic materials.Type: GrantFiled: July 27, 2016Date of Patent: July 30, 2019Assignee: YAZAKI CORPORATIONInventors: Osamu Kimura, Yoshinori Matsushita, Yasuhiro Okamoto
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Publication number: 20190198663Abstract: To improve characteristics of a semiconductor device. A first p-type semiconductor region having an impurity of a conductivity type opposite from that of a drift layer is arranged in the drift layer below a trench, and a second p-type semiconductor region is further arranged that is spaced at a distance from a region where the trench is formed as seen from above and that has the impurity of the conductivity type opposite from that of the drift layer. The second p-type semiconductor region is configured by a plurality of regions arranged at a space in a Y direction (depth direction in the drawings). Thus, it is possible to reduce the specific on-resistance while maintaining the breakdown voltage of the gate insulating film by providing the first and second p-type semiconductor regions and further by arranging the second p-type semiconductor region spaced by the space.Type: ApplicationFiled: November 15, 2018Publication date: June 27, 2019Inventors: Atsushi SAKAI, Katsumi EIKYU, Satoshi EGUCHI, Nobuo MACHIDA, Koichi ARAI, Yasuhiro OKAMOTO, Kenichi HISADA, Yasunori YAMASHITA
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Publication number: 20190150713Abstract: The disclosed technology is directed to an insertion apparatus comprises an insertion portion that includes a tubular body freely rotates around a longitudinal axis over an outer circumferential surface. The insertion portion is flexible and configured to be inserted into a body cavity. The insertion portion and a drive source configured to rotate the tubular body wherein the tubular body includes a first flexural rigidity. A part of the insertion portion includes a second flexural rigidity. The tubular body is mounted to the part. The tubular body and the part of the insertion portion includes a total flexural rigidity based on the first flexural rigidity and the second flexural rigidity so that bending of the tubular body is limited to a predetermined bending angle to avoid stop of rotation of the tubular body.Type: ApplicationFiled: January 24, 2019Publication date: May 23, 2019Applicant: Olympus CorporationInventor: Yasuhiro Okamoto
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Publication number: 20190150704Abstract: The disclosed technology is directed to an insertion apparatus comprises an insertion portion having a tubular body freely rotates around a longitudinal axis over an outer circumferential surface. The insertion portion is flexible and configured to be inserted into a body cavity. A drive source is configured to rotate the tubular body wherein a part of the insertion portion includes a predetermined flexural rigidity to which the tubular body being mounted thereto. The part of the insertion portion is formed of a structure that is configured in such a manner that bending of the tubular body is not caused beyond a predetermined bending angle so as to avoid stop of rotation of the tubular body by a driving force of the drive source even when an external force that intends to keep a bending shape of the body cavity is received from a wall of the body cavity in contact.Type: ApplicationFiled: January 24, 2019Publication date: May 23, 2019Applicant: Olympus CorporationInventor: Yasuhiro Okamoto
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Publication number: 20190104924Abstract: An insertion apparatus includes: an insertion portion which is inserted into a body cavity of a subject and detachably equipped with a spiral tube rotatable around a longitudinal axis, the insertion portion having predetermined flexibility; and a driving source configured to cause the spiral tube to rotate; and the spiral tube is configured with a structure set not to bend at an arbitrary bending angle or more, the arbitrary bending angle being an angle at which rotation of the spiral tube is not stopped by driving force of the driving source even if the spiral tube receives external force to try to maintain a bending shape from a touched body cavity wall.Type: ApplicationFiled: December 7, 2018Publication date: April 11, 2019Applicant: OLYMPUS CORPORATIONInventor: Yasuhiro OKAMOTO
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Patent number: 10249715Abstract: Properties of a semiconductor device are improved. A semiconductor device is configured so as to include a voltage clamp layer, a channel underlayer, a channel layer, and a barrier layer, which are formed in order above a substrate, a trench that extends up to the middle of the channel layer while penetrating through the barrier layer, a gate electrode disposed within the trench with a gate insulating film in between, a source electrode and a drain electrode formed above the barrier layer on both sides of the gate electrode, and a fourth electrode electrically coupled to the voltage clamp layer. The fourth electrode is electrically isolated from the source electrode, and a voltage applied to the fourth electrode is different from a voltage applied to the source electrode. Consequently, threshold control can be performed. For example, a threshold of a MISFET can be increased.Type: GrantFiled: May 25, 2017Date of Patent: April 2, 2019Assignee: Renesas Electronics CorporationInventors: Hironobu Miyamoto, Tatsuo Nakayama, Atsushi Tsuboi, Yasuhiro Okamoto, Hiroshi Kawaguchi
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Patent number: 10249727Abstract: In order to improve the characteristics of a semiconductor device including: a channel layer and a barrier layer formed above a substrate; and a gate electrode arranged over the barrier layer via a gate insulating film, the semiconductor device is configured as follows. A silicon nitride film is provided over the barrier layer between a source electrode and the gate electrode, and is also provided over the barrier layer between a drain electrode and the gate electrode GE. The surface potential of the barrier layer is reduced by the silicon nitride film, thereby allowing two-dimensional electron gas to be formed. Thus, by selectively forming two-dimensional electron gas only in a region where the silicon nitride film is formed, a normally-off operation can be performed even if a trench gate structure is not adopted.Type: GrantFiled: August 7, 2017Date of Patent: April 2, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Yasuhiro Okamoto