Patents by Inventor Yasuhiro Okamoto

Yasuhiro Okamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9660045
    Abstract: The characteristics of a semiconductor device are improved. A semiconductor device is formed so as to have a channel layer formed over a substrate, a barrier layer, a trench penetrating through the barrier layer in an opening region, and reaching some point of the channel layer, a gate electrode arranged in the trench via a gate insulation film, and an insulation film formed over the barrier layer outside the opening region. Then, the insulation film has a lamination structure of a Si-rich silicon nitride film, and a N-rich silicon nitride film situated thereunder. Thus, the upper layer of the insulation film is set as the Si-rich silicon nitride film. This enables the improvement of the breakdown voltage, and further, enables the improvement of the etching resistance. Whereas, the lower layer of the insulation film is set as the N-rich silicon nitride film. This can suppress collapse.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: May 23, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Takashi Inoue, Toshiyuki Takewaki, Tatsuo Nakayama, Yasuhiro Okamoto, Hironobu Miyamoto
  • Patent number: 9636001
    Abstract: An introduction device applies urging force linearly generated by a spring to a nut portion screwed to a drive shaft to convert the urging force to the rotation direction of the drive shaft. This conversion returns an RL operation dial provided at the end of the drive shaft in a direction opposite to the rotation direction in which the RL operation dial is operated, and then returns the RL operation dial to an original neutral position.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: May 2, 2017
    Assignee: OLYMPUS CORPORATION
    Inventor: Yasuhiro Okamoto
  • Publication number: 20170103898
    Abstract: A method of manufacturing a semiconductor device includes forming a first nitride semiconductor layer, forming thereover a second nitride semiconductor layer having a band gap wider than that of the first nitride semiconductor layer, and thereby forming a stacked body, etching the stacked body with a first film placed over the stacked body and including a first opening portion as a mask to form a trench penetrating through the second nitride semiconductor layer and reaching an inside of the first nitride semiconductor layer, causing an end portion of the first film to retreat from an end portion of the trench, forming a second film over the first film including the inside of the trench, and forming a gate electrode over the second film.
    Type: Application
    Filed: December 20, 2016
    Publication date: April 13, 2017
    Inventors: Takashi INOUE, Tatsuo Nakayama, Yasuhiro Okamoto, Hiroshi Kawaguchi, Toshiyuki Takewaki, Nobuhiro Nagura, Takayuki Nagai, Yoshinao Miura, Hironobu Miyamoto
  • Patent number: 9601609
    Abstract: Characteristics of a semiconductor device are improved. A semiconductor device includes a potential fixing layer, a channel underlayer, a channel layer, and a barrier layer formed above a substrate, a trench that penetrates the barrier layer and reaches as far as a middle of the channel layer, a gate electrode disposed by way of an insulation film in the trench, and a source electrode and a drain electrode formed respectively over the barrier layer on both sides of the gate electrode. A coupling portion inside the through hole that reaches as far as the potential fixing layer electrically couples the potential fixing layer and the source electrode. This can reduce fluctuation of the characteristics such as a threshold voltage and an on-resistance.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: March 21, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tatsuo Nakayama, Hironobu Miyamoto, Yasuhiro Okamoto, Yoshinao Miura, Takashi Inoue
  • Publication number: 20170054014
    Abstract: The semiconductor device includes a trench that penetrates a barrier layer, and reaches a middle portion of a channel layer among an n+ layer, an n-type layer, a p-type layer, the channel layer, and the barrier layer which are formed above a substrate, a gate electrode arranged within the groove through a gate insulating film, and a source electrode and a drain electrode which are formed above the barrier layer on both sides of the gate electrode. The n-type layer and the drain electrode are electrically coupled by a connection portion that reaches the n+ layer. The p-type layer and the source electrode are electrically coupled by a connection portion that reaches the p-type layer. A diode including a p-type layer and an n-type layer is provided between the source electrode and the drain electrode, to thereby prevent the breaking of an element caused by an avalanche breakdown.
    Type: Application
    Filed: November 8, 2016
    Publication date: February 23, 2017
    Inventors: Tatsuo Nakayama, Hironobu Miyamoto, Yasuhiro Okamoto, Yoshinao Miura, Takashi Inoue
  • Publication number: 20170028945
    Abstract: A wire harness to be installed in a vehicle includes an electric wire and a protective tube that protects the electric wire. The electric wire is provided at the lower part of a vehicle body of the vehicle and the protective tube covers the electric wire and includes ferromagnetic materials.
    Type: Application
    Filed: July 27, 2016
    Publication date: February 2, 2017
    Inventors: Osamu Kimura, Yoshinori Matsushita, Yasuhiro Okamoto
  • Patent number: 9559183
    Abstract: To provide a semiconductor device having improved characteristics. The semiconductor device has a substrate and thereon a buffer layer, a channel layer, a barrier layer, a trench penetrating therethrough and reaching the inside of the channel layer, a gate electrode placed in the trench via a gate insulating film, and drain and source electrodes on the barrier layer on both sides of the gate electrode. The gate insulating film has a first portion made of a first insulating film and extending from the end portion of the trench to the side of the drain electrode and a second portion made of first and second insulating films and placed on the side of the drain electrode relative to the first portion. The on resistance can be reduced by decreasing the thickness of the first portion at the end portion of the trench on the side of the drain electrode.
    Type: Grant
    Filed: May 6, 2014
    Date of Patent: January 31, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi Inoue, Tatsuo Nakayama, Yasuhiro Okamoto, Hiroshi Kawaguchi, Toshiyuki Takewaki, Nobuhiro Nagura, Takayuki Nagai, Yoshinao Miura, Hironobu Miyamoto
  • Publication number: 20170005189
    Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer formed over the first semiconductor layer, a third semiconductor layer formed over the second semiconductor layer, a gate electrode formed over the third semiconductor layer, and a gate insulating film formed between the third semiconductor layer and the gate electrode. The second semiconductor layer includes an Aly?1-yN layer (? includes Ga or In, and 0?y<1), and the third semiconductor layer includes an Alz?1-zN layer (0?z<1). y of the Aly?1-yN layer forming the second semiconductor layer increases from the third semiconductor layer to the first semiconductor layer at least in a region under the gate electrode. There is a relationship “z>y” at an interface between the second nitride semiconductor layer and the third nitride semiconductor layer.
    Type: Application
    Filed: September 14, 2016
    Publication date: January 5, 2017
    Inventors: Yasuhiro OKAMOTO, Tatsuo NAKAYAMA, Takashi INOUE, Hironobu MIYAMOTO
  • Patent number: 9536978
    Abstract: To improve performance of a semiconductor device. For example, on the assumption that a superlattice layer is inserted between a buffer layer and a channel layer, a concentration of acceptors introduced into nitride semiconductor layers forming a part of the superlattice layer is higher than a concentration of acceptors introduced into nitride semiconductor layers forming the other part of the superlattice layer. That is, the concentration of acceptors introduced into the nitride semiconductor layers having a small band gap is higher than the concentration of acceptors introduced into the nitride semiconductor layers having a large band gap.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: January 3, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsuo Nakayama, Hironobu Miyamoto, Yasuhiro Okamoto, Ryohei Nega, Masaaki Kanazawa, Takashi Inoue
  • Patent number: 9530879
    Abstract: A semiconductor device including a field effect transistor including a substrate, a lower barrier layer provided on the substrate, a channel layer provided on the lower barrier layer, an electron supplying layer provided on the channel layer, a source electrode and a drain electrode provided on the electron layer, and a gate electrode provided between the source electrode and the drain electrode. The lower barrier layer includes a composition of In1-zAlzN (0?z?1). The channel layer includes a composition of AlxGa1-xN (0?x?1). A recess is provided in a region between the source electrode and the drain electrode, wherein the recess goes through the electron supplying layer to a depth that exposes the channel layer, and the gate electrode is disposed on a gate insulating film that covers a bottom surface and an inner wall surface of the recess.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: December 27, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Yasuhiro Okamoto, Yuji Ando, Tatsuo Nakayama, Takashi Inoue, Kazuki Ota
  • Publication number: 20160367111
    Abstract: An endoscope includes a bending section being disposed in an insertion section, a plurality of towing members disposed in the insertion section and in an operation section from the bending section, a disk member turnably provided in the operation section and configured to turn to tow and loosen the plurality of towing members, the plurality of towing members being suspended in an outer circumference of the disk member, operation members turnably disposed in the operation section and configured to turn the disk member to bend the bending section, and a turning shaft configured to turnably axially support the disk member and the operation members with respect to the operation section in a position decentered to the distal end side by a predetermined distance d with respect to a center of the disk member in an initial state in which the bending section is linear.
    Type: Application
    Filed: August 31, 2016
    Publication date: December 22, 2016
    Applicant: OLYMPUS CORPORATION
    Inventor: Yasuhiro OKAMOTO
  • Patent number: 9520489
    Abstract: Characteristics of a semiconductor device are improved. The semiconductor device is configured to provide a trench that penetrates a barrier layer, and reaches a middle portion of a channel layer among an n+ layer, an n-type layer, a p-type layer, the channel layer, and the barrier layer which are formed above a substrate, a gate electrode arranged within the groove through a gate insulating film, and a source electrode and a drain electrode which are formed above the barrier layer on both sides of the gate electrode. The n-type layer and the drain electrode are electrically coupled to each other by a connection portion that reaches the n+ layer. The p-type layer and the source electrode are electrically coupled to each other by a connection portion that reaches the p-type layer. A diode including a p-type layer and an n-type layer is provided between the source electrode and the drain electrode, to thereby prevent the breaking of an element caused by an avalanche breakdown.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: December 13, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tatsuo Nakayama, Hironobu Miyamoto, Yasuhiro Okamoto, Yoshinao Miura, Takashi Inoue
  • Patent number: 9502551
    Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer formed over the first semiconductor layer, a gate insulating film contacting the second semiconductor layer, and a gate electrode facing the second semiconductor layer via the gate insulating film. The first semiconductor layer includes an Alx?1-xN layer (? includes Ga or In, and 0<x<1), and the second semiconductor layer includes an Aly?1-yN layer (0?y<1), in which y of the Aly?1-yN layer forming the second semiconductor layer increases at least in a region under the gate electrode as a position where y is measured approaches the first semiconductor layer.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: November 22, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yasuhiro Okamoto, Tatsuo Nakayama, Takashi Inoue, Hironobu Miyamoto
  • Publication number: 20160240648
    Abstract: A semiconductor device includes a first nitride semiconductor layer formed above a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer, a trench passing through the second nitride semiconductor layer and into the first nitride semiconductor layer, a gate insulation film formed in the trench, and a gate electrode disposed by way of the gate insulation film in an inside of the trench. The corner of the trench between a side wall of the trench and a bottom of the trench includes a rounded shape, and a corner of the gate insulation film in contact with the corner of the trench includes a rounded shape.
    Type: Application
    Filed: April 29, 2016
    Publication date: August 18, 2016
    Inventors: Yasuhiro OKAMOTO, Tatsuo NAKAYAMA, Takashi INOUE
  • Publication number: 20160233211
    Abstract: The ringing of a switching waveform of a semiconductor device is restrained. For example, an interconnect (L5) is laid which functions as a source of a power transistor (Q3) and a cathode of a diode (D4), and further functioning as a drain of a power transistor (Q4) and an anode of a diode (D3). In other words, a power transistor and a diode coupled to this power transistor in series are formed in the same semiconductor chip; and further an interconnect functioning as a drain of the power transistor and an interconnect functioning as an anode of the diode are made common to each other. This structure makes it possible to decrease a parasite inductance between the power transistor and the diode coupled to each other in series.
    Type: Application
    Filed: December 16, 2015
    Publication date: August 11, 2016
    Inventors: Yoshinao MIURA, Hironobu MIYAMOTO, Yasuhiro OKAMOTO
  • Publication number: 20160204243
    Abstract: The characteristics of a semiconductor device are improved. A semiconductor device is formed so as to have a channel layer formed over a substrate, a barrier layer, a trench penetrating through the barrier layer in an opening region, and reaching some point of the channel layer, a gate electrode arranged in the trench via a gate insulation film, and an insulation film formed over the barrier layer outside the opening region. Then, the insulation film has a lamination structure of a Si-rich silicon nitride film, and a N-rich silicon nitride film situated thereunder. Thus, the upper layer of the insulation film is set as the Si-rich silicon nitride film. This enables the improvement of the breakdown voltage, and further, enables the improvement of the etching resistance. Whereas, the lower layer of the insulation film is set as the N-rich silicon nitride film. This can suppress collapse.
    Type: Application
    Filed: March 24, 2016
    Publication date: July 14, 2016
    Inventors: Takashi INOUE, Toshiyuki TAKEWAKI, Tatsuo NAKAYAMA, Yasuhiro OKAMOTO, Hironobu MIYAMOTO
  • Publication number: 20160190294
    Abstract: In order to improve the characteristics of a semiconductor device including: a channel layer and a barrier layer formed above a substrate; and a gate electrode arranged over the barrier layer via a gate insulating film, the semiconductor device is configured as follows. A silicon nitride film is provided over the barrier layer between a source electrode and the gate electrode, and is also provided over the barrier layer between a drain electrode and the gate electrode GE. The surface potential of the barrier layer is reduced by the silicon nitride film, thereby allowing two-dimensional electron gas to be formed. Thus, by selectively forming two-dimensional electron gas only in a region where the silicon nitride film is formed, a normally-off operation can be performed even if a trench gate structure is not adopted.
    Type: Application
    Filed: December 7, 2015
    Publication date: June 30, 2016
    Inventor: Yasuhiro OKAMOTO
  • Publication number: 20160183769
    Abstract: An insertion instrument includes an insertion portion having a curving portion, and an operation portion body coupled to the proximal side of the insertion portion. The operation portion body includes a first surface, and a second surface extending from the first surface and extending in a direction different from the direction in which the first surface extends. A finger side other than a thumb of a grasping hand is located in the second surface. The operation portion body includes a first curving operation portion which is provided in the first surface and which curves the curving portion in a first direction, a functional switch which is provided in the second surface and which operates a predetermined function of the insertion instrument, and a second curving operation portion which is provided in the second surface.
    Type: Application
    Filed: March 4, 2016
    Publication date: June 30, 2016
    Applicant: OLYMPUS CORPORATION
    Inventor: Yasuhiro OKAMOTO
  • Patent number: 9375135
    Abstract: An insertion device includes a UD knob having an outer peripheral side notched in a concave recess with such a curvature and a size as to come in close contact with a base part of a thumb, and an RL knob placed on the UD knob with the same center of rotation, and is configured such that the thumb extends beyond the UD knob, the base part of the thumb is put in contact with a deepest part of the recess of the UD knob, and the RL knob is operably present within a movable range of the thumb beyond the UD knob. The RL knob is configured to be driven by a motor, and thereby the RL knob is rotated by a fingertip to bend a bend portion.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: June 28, 2016
    Assignee: OLYMPUS CORPORATION
    Inventor: Yasuhiro Okamoto
  • Patent number: 9375799
    Abstract: A multi-wire electrical discharge machining system for slicing a workpiece into a thin leaf at intervals of a plurality of wires arranged together causes the wires arranged together to travel in the same direction and includes a power feed contact configured to collectively comes into contact with the traveling wires, a machining power supply portion configured to supply a machining power supply to the power feed contact, and an electrical discharge portion configured to electrically discharge a machining power supply in which the traveling wires comes into contact with the power feed contact to collectively supply power to the traveling wires to the workpiece, in which a resistance between the machining power supply portion and the power feed contact is smaller than a resistance between the power feed contact and the electrical discharge portion.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: June 28, 2016
    Assignees: CANON MARKETING JAPAN KABUSHIKI KAISHA, KABUSHIKI KAISHA MAKINO HURAISU SEISAKUSHO
    Inventors: Yasuhiro Okamoto, Akira Okada, Haruya Kurihara