Patents by Inventor Yasuhiro Takeda

Yasuhiro Takeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9446350
    Abstract: [Object] To provide a gas decomposition apparatus and a gas decomposition method in which no safety problems occur in spite of the application of a relatively high voltage between an anode and a cathode for the purpose of decomposing odorous gases of many types. [Solution] A catalytic electrode layer 6 that contains a catalyst and is porous; a counter electrode layer 7 that forms a pair with the catalytic electrode; and an electrolyte layer 15 that is sandwiched between the catalytic electrode and the counter electrode and has ion conductivity are included. The catalyst is held by the catalytic electrode in the form of being carried by a carrier containing a conductive material or the catalyst is directly carried by the catalytic electrode. A conductive material in the catalytic electrode, the conductive material being in contact with the catalyst, is not a noncovalent carbon material.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: September 20, 2016
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Masatoshi Majima, Shinji Inazawa, Koji Nitta, Masahiro Yamakawa, Takayasu Sugihara, Yasuhiro Takeda, Yoshihiro Akahane, Takahiro Imai
  • Publication number: 20160093555
    Abstract: The TSV technology has been popular as one of stacking technologies of a plurality of semiconductor chips. It has however been revealed by the present inventors that when TSV is formed using a so-called first via process, via middle process, front-via via last process, or the like, there is a possibility of defects such as gate breakdown occurring due to electrostatic breakdown in the subsequent process. In order to overcome the above problem, the present invention provides a method of manufacturing a semiconductor integrated circuit device, in which a through via electrode is formed by forming a hole in a semiconductor substrate, forming an insulating member in the hole, and burying a conductive member in the resulting hole while covering a portion of the hole except for the bottom portion with the insulating member.
    Type: Application
    Filed: December 8, 2015
    Publication date: March 31, 2016
    Applicant: Renesas Electronics Corporation
    Inventors: Yasuhiro TAKEDA, Takao KUMIHASHI, Hiroshi YANAGITA, Takashi TAKEUCHI, Yasushi MATSUDA
  • Patent number: 9240330
    Abstract: The TSV technology has been popular as one of stacking technologies of a plurality of semiconductor chips. It has however been revealed by the present inventors that when TSV is formed using a so-called first via process, via middle process, front-via via last process, or the like, there is a possibility of defects such as gate breakdown occurring due to electrostatic breakdown in the subsequent process. In order to overcome the above problem, the present invention provides a method of manufacturing a semiconductor integrated circuit device, in which a through via electrode is formed by forming a hole in a semiconductor substrate, forming an insulating member in the hole, and burying a conductive member in the resulting hole while covering a portion of the hole except for the bottom portion with the insulating member.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: January 19, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Yasuhiro Takeda, Takao Kumihashi, Hiroshi Yanagita, Takashi Takeuchi, Yasushi Matsuda
  • Publication number: 20150333139
    Abstract: An object is to provide a semiconductor device having improved reliability by preventing, in forming a nonvolatile memory and MOSFETS on the same substrate, an increase in the size of grains in a gate electrode. The object can be achieved by forming the control gate electrode of the nonvolatile memory and the gate electrodes of the other MOSFETs from films of the same layer, respectively, and configuring each of the control gate electrode and the gate electrodes from a stack of two polysilicon film layers.
    Type: Application
    Filed: July 18, 2015
    Publication date: November 19, 2015
    Inventors: Hiroshi Uozaki, Yasuhiro Takeda, Keiichi Maekawa, Takumi Hasegawa, Kota Funayama, Yoshiki Maruyama, Kazutoshi Shiba, Shuichi Kudo
  • Patent number: 9099552
    Abstract: The invention provides an LDMOS transistor of which the time-dependent degrading of the performance due to the trapping of hot electrons in the gate insulation film is decreased. A body layer is disposed in a surface portion of an N? type semiconductor layer. A source layer including an N? type layer is disposed in a surface portion of the body layer. An N? type drift layer is formed in a surface portion of the N? type semiconductor layer. This drift layer includes a first region having a first N type impurity concentration peak region and a second region having a second N type impurity concentration peak region that is positioned deeper than the first N type impurity concentration peak region, the second region adjoining this first region. An N+ type drain layer is formed in a surface portion of the second region.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: August 4, 2015
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yasuhiro Takeda, Shinya Inoue, Yuzo Otsuru
  • Patent number: 9093546
    Abstract: An object is to provide a semiconductor device having improved reliability by preventing, in forming a nonvolatile memory and MOSFETS on the same substrate, an increase in the size of grains in a gate electrode. The object can be achieved by forming the control gate electrode of the nonvolatile memory and the gate electrodes of the other MOSFETs from films of the same layer, respectively, and configuring each of the control gate electrode and the gate electrodes from a stack of two polysilicon film layers.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: July 28, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Uozaki, Yasuhiro Takeda, Keiichi Maekawa, Takumi Hasegawa, Kota Funayama, Yoshiki Maruyama, Kazutoshi Shiba, Shuichi Kudo
  • Publication number: 20150080125
    Abstract: There is provided an information processing apparatus including an attribute management unit configured to manage a variable attribute value associated with each one or more characters existing in a real space, a detection unit configured to detect an interaction event between a first character and a real object by using an image captured by a camera that captures the real space, and a setting unit configured to set a rule for changing the attribute value of the first character depending on the interaction event. In a case where the detection unit has detected the interaction event, the attribute management unit changes the attribute value of the first character in accordance with the rule set by the setting unit.
    Type: Application
    Filed: March 7, 2013
    Publication date: March 19, 2015
    Inventors: Alexis Andre, Akichika Tanaka, Yasuhiro Takeda, Tetsu Natsume, Kenichi Okada, Takatoshi Nakamura
  • Patent number: 8916931
    Abstract: An N type layer made of an N type epitaxial layer in which an N+ type drain layer etc are formed is surrounded by a P type drain isolation layer extending from the front surface of the N type epitaxial layer to an N+ type buried layer. A P type collector layer is formed in an N type layer made of the N type epitaxial layer surrounded by the P type drain isolation layer and a P type element isolation layer, extending from the front surface to the inside of the N type layer. A parasitic bipolar transistor that uses the first conductive type drain isolation layer as the emitter, the second conductive type N type layer as the base, and the collector layer as the collector is thus formed so as to flow a surge current into a ground line.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: December 23, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Yasuhiro Takeda, Seiji Otake
  • Publication number: 20140247527
    Abstract: An ESD protection element can have a high ESD protection characteristic which has a desired breakdown voltage and flows a large discharge current. A junction diode is formed by an N+ type buried layer having a proper impurity concentration and a P+ type buried layer. The P+ type buried layer is combined with a P+ type drawing layer to penetrate an N? type epitaxial layer and be connected to an anode element. An N+ type diffusion layer and a P+ typed diffusion layer connected to an surrounding the N+ type diffusion layer are formed in the N? epitaxial layer surrounded by the P+ type buried layer etc. The N+ type diffusion layer and P+ type diffusion layer are connected to a cathode electrode. An ESD protection element is formed by the PN junction diode and a parasitic PNP bipolar transistor which uses the P+ type diffusion layer as an emitted, the N? type epitaxial layer as the base, and the P+ type drawing layer etc. as the collector.
    Type: Application
    Filed: May 16, 2014
    Publication date: September 4, 2014
    Applicant: Semiconductor Components Industries, LLC
    Inventors: Seiji OTAKE, Yasuhiro TAKEDA, Yuta MIYAMOTO
  • Publication number: 20140181748
    Abstract: There is provided an information processing apparatus, including an icon display section which displays an icon associated to an action of a user for a purpose of the user, a selection condition acquisition section which acquires a selection condition of the icon displayed by the icon display section, and a display information generation section which generates display information for sharing selected action associated to the icon with another user by using the selection condition acquired by the selection condition acquisition section.
    Type: Application
    Filed: October 29, 2013
    Publication date: June 26, 2014
    Applicant: Sony Corporation
    Inventor: Yasuhiro Takeda
  • Publication number: 20140167159
    Abstract: The invention provides an LDMOS transistor of which the time-dependent degrading of the performance due to the trapping of hot electrons in the gate insulation film is decreased. A body layer is disposed in a surface portion of an N?-type semiconductor layer. A source layer including an N?-type layer is disposed in a surface portion of the body layer. An N? type drift layer is formed in a surface portion of the N?-type semiconductor layer. This drift layer includes a first region having a first N type impurity concentration peak region and a second region having a second N type impurity concentration peak region that is positioned deeper than the first N type impurity concentration peak region, the second region adjoining this first region. An N+ type drain layer is formed in a surface portion of the second region.
    Type: Application
    Filed: February 24, 2014
    Publication date: June 19, 2014
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yasuhiro Takeda, Shinya Inoue, Yuzo Otsuru
  • Patent number: 8754479
    Abstract: An ESD protection element is formed by a PN junction diode including an N+ type buried layer having a proper impurity concentration and a P+ type buried layer and a parasitic PNP bipolar transistor which uses a P+ type drawing layer connected to a P+ type diffusion layer as the emitter, an N? type epitaxial layer as the base, and a P type semiconductor substrate as the collector. The P+ type buried layer is connected to an anode electrode, and the P+ type diffusion layer and an N+ type diffusion layer connected to and surrounding the P+ type diffusion layer are connected to a cathode electrode. When a large positive static electricity is applied to the cathode electrode, the parasitic PNP bipolar transistor turns on to flow a large discharge current.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: June 17, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Seiji Otake, Yasuhiro Takeda, Yuta Miyamoto
  • Publication number: 20140138758
    Abstract: An object is to provide a semiconductor device having improved reliability by preventing, in forming a nonvolatile memory and MOSFETS on the same substrate, an increase in the size of grains in a gate electrode. The object can be achieved by forming the control gate electrode of the nonvolatile memory and the gate electrodes of the other MOSFETs from films of the same layer, respectively, and configuring each of the control gate electrode and the gate electrodes from a stack of two polysilicon film layers.
    Type: Application
    Filed: October 30, 2013
    Publication date: May 22, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Hiroshi Uozaki, Yasuhiro Takeda, Keiichi Maekawa, Takumi Hasegawa, Kota Funayama, Yoshiki Maruyama, Kazutoshi Shiba, Shuichi Kudo
  • Publication number: 20140102913
    Abstract: [Object] To provide a gas decomposition apparatus and a gas decomposition method in which no safety problems occur in spite of the application of a relatively high voltage between an anode and a cathode for the purpose of decomposing odorous gases of many types. [Solution] A catalytic electrode layer 6 that contains a catalyst and is porous; a counter electrode layer 7 that forms a pair with the catalytic electrode; and an electrolyte layer 15 that is sandwiched between the catalytic electrode and the counter electrode and has ion conductivity are included. The catalyst is held by the catalytic electrode in the form of being carried by a carrier containing a conductive material or the catalyst is directly carried by the catalytic electrode. A conductive material in the catalytic electrode, the conductive material being in contact with the catalyst, is not a noncovalent carbon material.
    Type: Application
    Filed: December 19, 2013
    Publication date: April 17, 2014
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Masatoshi MAJIMA, Shinji INAZAWA, Koji NITTA, Masahiro YAMAKAWA, Takayasu SUGIHARA, Yasuhiro TAKEDA, Yoshihiro AKAHANE, Takahiro IMAI
  • Patent number: 8698236
    Abstract: The invention provides an LDMOS transistor of which the time-dependent degrading of the performance due to the trapping of hot electrons in the gate insulation film is decreased. A body layer is disposed in a surface portion of an N?? type semiconductor layer. A source layer including an N? type layer is disposed in a surface portion of the body layer. An N? type drift layer is formed in a surface portion of the N?? type semiconductor layer. This drift layer includes a first region having a first N type impurity concentration peak region and a second region having a second N type impurity concentration peak region that is positioned deeper than the first N type impurity concentration peak region, the second region adjoining this first region. An N+ type drain layer is formed in a surface portion of the second region.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: April 15, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Yasuhiro Takeda, Shinya Inoue, Yuzo Otsuru
  • Patent number: 8692330
    Abstract: A semiconductor device equally turns on the parasitic bipolar transistors in the finger portions of the finger form source and drain electrodes when a surge voltage is applied, even with the P+ type contact layer surrounding the N+ type source layers and the N+ type drain layers connected to the finger form source and drain electrodes. A P+ type contact layer surrounds N+ type source layers and N+ type drain layers. Metal silicide layers are formed on the N+ type source layers, the N+ type drain layers, and a portion of the P+ type contact layer. Finger form source electrodes, finger form drain electrodes, and a P+ type contact electrode surrounding these finger form electrodes are formed, being connected to the metal silicide layers respectively through contact holes formed in an interlayer insulation film deposited on the metal silicide layers.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: April 8, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Yuzo Otsuru, Yasuhiro Takeda, Shigeyuki Sugihara, Shinya Inoue
  • Patent number: 8657496
    Abstract: A spout member including a base portion which is fixed to a bag body, a cylindrical portion which protrudes upward from the base portion, and a sealing portion which seals a front end of the cylindrical portion through a breakable thin portion is disposed between two sheets of film forming the bag body. A sealing chamber accommodating the cylindrical portion and the sealing portion is opened by tearing the two sheets of film along an opening assisting line. An opening assisting plate protruding to at least one of a left side and a right side of the sealing portion is disposed above the opening assisting line. A sandwiching reinforcement seal portion for reinforcing the two sheets of film by sealing inner surfaces thereof is provided between the opening assisting plate and the opening assisting line.
    Type: Grant
    Filed: December 3, 2009
    Date of Patent: February 25, 2014
    Assignees: Morinaga Milk Industry Co., Ltd., Fujimori Kogyo Co., Ltd.
    Inventors: Yasuhiro Takeda, Kenji Washida, Takahiro Koyama, Junichi Hashimoto, Matsutarou Ono, Yasuharu Takada, Toshihiko Mori, Moritoshi Oguni
  • Patent number: 8641887
    Abstract: [Object] To provide a gas decomposition apparatus and a gas decomposition method in which no safety problems occur in spite of the application of a relatively high voltage between an anode and a cathode for the purpose of decomposing odorous gases of many types. [Solution] A catalytic electrode layer 6 that contains a catalyst and is porous; a counter electrode layer 7 that forms a pair with the catalytic electrode; and an electrolyte layer 15 that is sandwiched between the catalytic electrode and the counter electrode and has ion conductivity are included. The catalyst is held by the catalytic electrode in the form of being carried by a carrier containing a conductive material or the catalyst is directly carried by the catalytic electrode. A conductive material in the catalytic electrode, the conductive material being in contact with the catalyst, is not a noncovalent carbon material.
    Type: Grant
    Filed: April 2, 2009
    Date of Patent: February 4, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Masatoshi Majima, Shinji Inazawa, Koji Nitta, Masahiro Yamakawa, Takayasu Sugihara, Yasuhiro Takeda, Yoshihiro Akahane, Takahiro Imai
  • Patent number: 8618584
    Abstract: An ESD protection element is formed by a PN junction diode including an N+ type buried layer having a proper impurity concentration and a first P+ type buried layer and a parasitic PNP bipolar transistor which uses a second P+ type buried layer connected to a P+ type diffusion layer as the emitter, an N? type epitaxial layer as the base, and the first P+ type buried layer as the collector. The first P+ type buried layer is connected to an anode electrode, and the P+ type diffusion layer and an N+ type diffusion layer surrounding the P+ type diffusion layer are connected to a cathode electrode. When a large positive static electricity is applied to the cathode electrode, and the parasitic PNP bipolar transistor turns on to flow a large discharge current.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: December 31, 2013
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Seiji Otake, Yasuhiro Takeda, Yuta Miyamoto
  • Publication number: 20130252416
    Abstract: The TSV technology has been popular as one of stacking technologies of a plurality of semiconductor chips. It has however been revealed by the present inventors that when TSV is formed using a so-called first via process, via middle process, front-via via last process, or the like, there is a possibility of defects such as gate breakdown occurring due to electrostatic breakdown in the subsequent process. In order to overcome the above problem, the present invention provides a method of manufacturing a semiconductor integrated circuit device, in which a through via electrode is formed by forming a hole in a semiconductor substrate, forming an insulating member in the hole, and burying a conductive member in the resulting hole while covering a portion of the hole except for the bottom portion with the insulating member.
    Type: Application
    Filed: March 12, 2013
    Publication date: September 26, 2013
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Yasuhiro TAKEDA, Takao KUMIHASHI, Hiroshi YANAGITA, Takashi TAKEUCHI, Yasushi MATSUDA