Patents by Inventor Yasuhiro Taniguchi

Yasuhiro Taniguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7601581
    Abstract: Provided is a manufacturing method of a semiconductor device, which comprises forming a film stack of a gate insulating film, a charge storage film, insulating film, polysilicon film, silicon oxide film, silicon nitride film and cap insulating film over a semiconductor substrate; removing the film stack by photolithography and etching from a low breakdown voltage MISFET formation region and a high breakdown voltage MISFET formation region; forming gate insulating films, polysilicon film and cap insulating film over the semiconductor substrate, forming a gate electrode in the low breakdown voltage MISFET formation region and high breakdown voltage MISFET formation region, and then forming a gate electrode in a memory cell formation region. By the manufacturing technology of a semiconductor device for forming the gate electrodes of a first MISFET and a second MISFET in different steps, the present invention makes it possible to provide the first MISFET and the second MISFET each having improved reliability.
    Type: Grant
    Filed: January 5, 2007
    Date of Patent: October 13, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Yasuhiro Taniguchi, Kazuyoshi Shiba
  • Patent number: 7550809
    Abstract: A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transistor having a gate insulating film formed over a second element forming region of the main surface of the semiconductor substrate and made thinner than the gate insulating film of the first field effect transistor.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: June 23, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Shoji Shukuri, Norio Suzuki, Yasuhiro Taniguchi
  • Publication number: 20090154253
    Abstract: Provided is a nonvolatile memory with less element deterioration and good data retaining properties. In a nonvolatile memory formed by the manufacturing steps of a complementary type MISFET without adding thereto another additional step, erasing of data is carried out by applying 9V to an n type well, 9V to a p type semiconductor region, and ?9V to another p type semiconductor region and setting the source and drain of data writing and erasing MISFETs and data reading MISFETs at open potential to emit electrons from a gate electrode to a p well by FN tunneling. At this time, by applying a negative voltage to the p well having a capacitive element formed thereover and applying a positive voltage to the p well having the MISFETs formed thereover, a potential difference necessary for data erasing operation can be secured at a voltage low enough not to cause gate breakage.
    Type: Application
    Filed: November 13, 2008
    Publication date: June 18, 2009
    Inventors: Kazuyoshi SHIBA, Yasuhiro Taniguchi, Yasushi Oka
  • Patent number: 7466599
    Abstract: Provided is a nonvolatile memory with less element deterioration and good data retaining properties. In a nonvolatile memory formed by the manufacturing steps of a complementary type MISFET without adding thereto another additional step, erasing of data is carried out by applying 9V to an n type well, 9V to a p type semiconductor region, and ?9V to another p type semiconductor region and setting the source and drain of data writing and erasing MISFETs and data reading MISFETs at open potential to emit electrons from a gate electrode to a p well by FN tunneling. At this time, by applying a negative voltage to the p well having a capacitive element formed thereover and applying a positive voltage to the p well having the MISFETs formed thereover, a potential difference necessary for data erasing operation can be secured at a voltage low enough not to cause gate breakage.
    Type: Grant
    Filed: October 26, 2007
    Date of Patent: December 16, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Kazuyoshi Shiba, Yasuhiro Taniguchi, Yasushi Oka
  • Patent number: 7402873
    Abstract: A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transistor having a gate insulating film formed over a second element forming region of the main surface of the semiconductor substrate and made thinner than the gate insulating film of the first field effect transistor.
    Type: Grant
    Filed: July 6, 2007
    Date of Patent: July 22, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Shoji Shukuri, Norio Suzuki, Yasuhiro Taniguchi
  • Publication number: 20080141181
    Abstract: According to one embodiment, there is provided an information processing apparatus. A hand-shape database stores first data representing a first hand shape and second data representing a second hand shape. A hand-shape recognition unit determines whether a received image includes one of the first and second hand shapes. The hand-shape recognition unit outputs first predetermined information when the image includes the first hand shape, and outputs second predetermined information when the image includes the second hand shape. When the first predetermined information is received, a gesture interpretation unit displays on a display a user interface including display items each associated with an executable function, and selects one of the display items in accordance with the position information. When the second predetermined information is received in a state where one of the display items is selected, the gesture interpretation unit executes the function associated with the selected display item.
    Type: Application
    Filed: December 6, 2007
    Publication date: June 12, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: SATORU ISHIGAKI, Tsukasa Ike, Yasuhiro Taniguchi, Hisashi Kazama
  • Publication number: 20080056011
    Abstract: Provided is a nonvolatile memory with less element deterioration and good data retaining properties. In a nonvolatile memory formed by the manufacturing steps of a complementary type MISFET without adding thereto another additional step, erasing of data is carried out by applying 9V to an n type well, 9V to a p type semiconductor region, and ?9V to another p type semiconductor region and setting the source and drain of data writing and erasing MISFETs and data reading MISFETs at open potential to emit electrons from a gate electrode to a p well by FN tunneling. At this time, by applying a negative voltage to the p well having a capacitive element formed thereover and applying a positive voltage to the p well having the MISFETs formed thereover, a potential difference necessary for data erasing operation can be secured at a voltage low enough not to cause gate breakage.
    Type: Application
    Filed: October 26, 2007
    Publication date: March 6, 2008
    Inventors: Kazuyoshi Shiba, Yasuhiro Taniguchi, Yasushi Oka
  • Publication number: 20080052643
    Abstract: An apparatus for a user to interface with a control object apparatus by a posture or a motion of the user's physical part. An image input unit inputs an image including the user's physical part. A gesture recognition unit recognizes the posture or the motion of the user's physical part from the image. A control unit controls the control object apparatus based on an indication corresponding to the posture or the motion. A gesture information display unit displays an exemplary image of the posture or the motion recognized for the user's reference to indicate the control object apparatus.
    Type: Application
    Filed: June 1, 2007
    Publication date: February 28, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsukasa IKE, Yasuhiro Taniguchi, Ryuzo Okada, Nobuhisa Kishikawa, Kentaro Yokoi, Mayumi Yuasa, Bjorn Stenger
  • Patent number: 7321839
    Abstract: A first mirror and a second mirror are disposed in such a manner that their reflective surfaces are parallel and face toward each other. A mark is drawn between the first mirror and the second mirror. An image of the reflections of the mark in the first mirror and the second mirror is captured with a camera. Calibration of the camera system is performed based on the image.
    Type: Grant
    Filed: August 28, 2006
    Date of Patent: January 22, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichi Maeda, Yasuhiro Taniguchi, Susumu Kubota, Hiroaki Nakai
  • Publication number: 20070296030
    Abstract: A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transistor having a gate insulating film formed over a second element forming region of the main surface of the semiconductor substrate and made thinner than the gate insulating film of the first field effect transistor.
    Type: Application
    Filed: August 31, 2007
    Publication date: December 27, 2007
    Inventors: Shoji SHUKURI, Norio Suzuki, Yasuhiro Taniguchi
  • Patent number: 7313026
    Abstract: Provided is a nonvolatile memory with less element deterioration and good data retaining properties. In a nonvolatile memory formed by the manufacturing steps of a complementary type MISFET without adding thereto another additional step, erasing of data is carried out by applying 9V to an n type well, 9V to a p type semiconductor region, and ?9V to another p type semiconductor region and setting the source and drain of data writing and erasing MISFETs and data reading MISFETs at open potential to emit electrons from a gate electrode to a p well by FN tunneling. At this time, by applying a negative voltage to the p well having a capacitive element formed thereover and applying a positive voltage to the p well having the MISFETs formed thereover, a potential difference necessary for data erasing operation can be secured at a voltage low enough not to cause gate breakage.
    Type: Grant
    Filed: August 19, 2005
    Date of Patent: December 25, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Kazuyoshi Shiba, Yasuhiro Taniguchi, Yasushi Oka
  • Publication number: 20070290275
    Abstract: A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transistor having a gate insulating film formed over a second element forming region of the main surface of the semiconductor substrate and made thinner than the gate insulating film of the first field effect transistor.
    Type: Application
    Filed: July 6, 2007
    Publication date: December 20, 2007
    Inventors: Shoji Shukuri, Norio Suzuki, Yasuhiro Taniguchi
  • Publication number: 20070215917
    Abstract: Provided is a technology capable of manufacturing, in a short TAT, a mask ROM having a small memory cell area and high reliability. According to the manufacturing method of a semiconductor integrated circuit device according to the present invention, a memory cell is formed of a first MISFET equipped with an n type gate electrode composed of a polycrystalline silicon film having an n conductivity type impurity introduced therein and a second MISFET equipped with a p type gate electrode composed of a polycrystalline silicon film having a p conductivity type impurity introduced therein. In the n type gate electrode and p type gate electrode, an n conductivity type impurity is introduced further, whereby a threshold voltage of the first MISFET is made lower than that of the second MISFET.
    Type: Application
    Filed: January 29, 2007
    Publication date: September 20, 2007
    Inventor: Yasuhiro Taniguchi
  • Patent number: 7268401
    Abstract: A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transistor having a gate insulating film formed over a second element forming region of the main surface of the semiconductor substrate and made thinner than the gate insulating film of the first field effect transistor.
    Type: Grant
    Filed: August 17, 2006
    Date of Patent: September 11, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Shoji Shukuri, Norio Suzuki, Yasuhiro Taniguchi
  • Publication number: 20070207575
    Abstract: Provided is a manufacturing method of a semiconductor device, which comprises forming a film stack of a gate insulating film, a charge storage film, insulating film, polysilicon film, silicon oxide film, silicon nitride film and cap insulating film over a semiconductor substrate; removing the film stack by photolithography and etching from a low breakdown voltage MISFET formation region and a high breakdown voltage MISFET formation region; forming gate insulating films, polysilicon film and cap insulating film over the semiconductor substrate, forming a gate electrode in the low breakdown voltage MISFET formation region and high breakdown voltage MISFET formation region, and then forming a gate electrode in a memory cell formation region. By the manufacturing technology of a semiconductor device for forming the gate electrodes of a first MISFET and a second MISFET in different steps, the present invention makes it possible to provide the first MISFET and the second MISFET each having improved reliability.
    Type: Application
    Filed: January 5, 2007
    Publication date: September 6, 2007
    Inventors: Yasuhiro Taniguchi, Kazuyoshi Shiba
  • Publication number: 20070058838
    Abstract: An object position detecting apparatus includes range sensors, each sensing an object within a sensing region and obtaining an object information indicating existence of the object, image capturing units, each capturing an image data for the sensing region, a distance calculating unit that calculates approximate values of distances from the respective range sensors to the object using the object information and a position determing unit that determines a candidate region where the object exists in the image data based on the approximate values of the distances, and determines a position of the object in the image data by performing image processing of the image data and evaluating a result of the image processing based on a different predetermined threshold between an inside and an outside of the candidate region.
    Type: Application
    Filed: July 14, 2006
    Publication date: March 15, 2007
    Inventor: Yasuhiro Taniguchi
  • Patent number: 7166893
    Abstract: A MISFET capable of a high speed operation includes a metal silicide layer in a high concentration region aligned with a gate side wall layer on a self-alignment basis. A MISFET which can be driven at a high voltage includes an LDD portion having a width greater than the width of the side wall layer, a high concentration region in contact with the LDD portion and a metal silicide layer in the high concentration region.
    Type: Grant
    Filed: September 23, 2002
    Date of Patent: January 23, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Yasuhiro Taniguchi, Shoji Shukuri, Kenichi Kuroda, Shuji Ikeda, Takashi Hashimoto
  • Publication number: 20070005293
    Abstract: A first mirror and a second mirror are disposed in such a manner that their reflective surfaces are parallel and face toward each other. A mark is drawn between the first mirror and the second mirror. An image of the reflections of the mark in the first mirror and the second mirror is captured with a camera. Calibration of the camera system is performed based on the image.
    Type: Application
    Filed: August 28, 2006
    Publication date: January 4, 2007
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kenichi Maeda, Yasuhiro Taniguchi, Susumu Kubota, Hiroaki Nakai
  • Publication number: 20060273406
    Abstract: A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transistor having a gate insulating film formed over a second element forming region of the main surface of the semiconductor substrate and made thinner than the gate insulating film of the first field effect transistor.
    Type: Application
    Filed: August 17, 2006
    Publication date: December 7, 2006
    Inventors: Shoji Shukuri, Norio Suzuki, Yasuhiro Taniguchi
  • Patent number: RE39550
    Abstract: A security apparatus. A service is supplied to a user while maintaining the security of the service. A person discrimination section discriminates the user to be supplied the service. A user situation decision section decides whether the user is under a situation to use the service. An infringement situation decision section detects whether a non-user intrudes into a use area of the service in order to decide whether the security of the service is infringed. A service control section supplies the service to the user in case the person discrimination section discriminates the user, and controls a supply of the service if the use situation decision section decides the user is not under the situation to use the service or the infringement situation decision section decides that the security of the service is infringed.
    Type: Grant
    Filed: June 13, 2001
    Date of Patent: April 3, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kaoru Suzuki, Kazuhiro Fukui, Hisashi Kazama, Osamu Yamaguchi, Eiji Tanaka, Yasuhiro Taniguchi