Patents by Inventor Yasuhiro Taniguchi

Yasuhiro Taniguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7123539
    Abstract: A memory cell module comprises a memory cell array formed by memory cells of M columns×N rows. Each memory cell includes a magnetoresistive element or a magnetresistive element with a semiconductor element. A memory module comprises a first access means to access the memory cell array by a column direction and a second access means to access the memory cell array by a row direction. In this manner, data is read from a magnetoresistive memory module in both row and column directions.
    Type: Grant
    Filed: July 14, 2005
    Date of Patent: October 17, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Fujisaki, Kentaro Nakajima, Takeshi Chujoh, Yasuhiro Taniguchi
  • Patent number: 7124046
    Abstract: A first mirror and a second mirror are disposed in such a manner that their reflective surfaces are parallel and face toward each other. A mark is drawn between the first mirror and the second mirror. An image of the reflections of the mark in the first mirror and the second mirror is captured with a camera. Calibration of the camera system is performed based on the image.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: October 17, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichi Maeda, Yasuhiro Taniguchi, Susumu Kubota, Hiroaki Nakai
  • Patent number: 7119406
    Abstract: A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transistor having a gate insulating film formed over a second element forming region of the main surface of the semiconductor substrate and made thinner than the gate insulating film of the first field effect transistor.
    Type: Grant
    Filed: July 12, 2005
    Date of Patent: October 10, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Shoji Shukuri, Norio Suzuki, Yasuhiro Taniguchi
  • Patent number: 7095432
    Abstract: An image input unit inputs a plurality of images in a time series. Each input image includes a boundary line extending toward a vanishing point on a plane. A reverse projection image generation unit generates a reverse projection image of each input image by projecting information related to each input image onto the plane. A boundary line detection unit detects the boundary line from the reverse projection image by identifying a boundary line candidate on each reverse projection image.
    Type: Grant
    Filed: July 17, 2002
    Date of Patent: August 22, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiromitsu Nakayama, Susumu Kubota, Yasuhiro Taniguchi
  • Publication number: 20060138568
    Abstract: A MISFET capable of a high speed operation includes a metal silicide layer in a high concentration region aligned with a gate side wall layer on a self-alignment basis. A MISFET which can be driven at a high voltage includes an LDD portion having a width greater than the width of the side wall layer, a high concentration region in contact with the LDD portion and a metal silicide layer in the high concentration region.
    Type: Application
    Filed: February 23, 2006
    Publication date: June 29, 2006
    Inventors: Yasuhiro Taniguchi, Shoji Shukuri, Kenichi Kuroda, Shuji Ikeda, Takashi Hashimoto
  • Patent number: 7023062
    Abstract: A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transistor having a gate insulating film formed over a second element forming region of the main surface of the semiconductor substrate and made thinner than the gate insulating film of the first field effect transistor.
    Type: Grant
    Filed: August 7, 2003
    Date of Patent: April 4, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Shoji Shukuri, Norio Suzuki, Yasuhiro Taniguchi
  • Publication number: 20060050566
    Abstract: Provided is a nonvolatile memory with less element deterioration and good data retaining properties. In a nonvolatile memory formed by the manufacturing steps of a complementary type MISFET without adding thereto another additional step, erasing of data is carried out by applying 9V to an n type well, 9V to a p type semiconductor region, and ?9V to another p type semiconductor region and setting the source and drain of data writing and erasing MISFETs and data reading MISFETs at open potential to emit electrons from a gate electrode to a p well by FN tunneling. At this time, by applying a negative voltage to the p well having a capacitive element formed thereover and applying a positive voltage to the p well having the MISFETs formed thereover, a potential difference necessary for data erasing operation can be secured at a voltage low enough not to cause gate breakage.
    Type: Application
    Filed: August 19, 2005
    Publication date: March 9, 2006
    Inventors: Kazuyoshi Shiba, Yasuhiro Taniguchi, Yasushi Oka
  • Publication number: 20050249029
    Abstract: A memory cell module comprises a memory cell array formed by memory cells of M columns×N rows. Each memory cell includes a magnetoresistive element or a magnetresistive element with a semiconductor element. A memory module comprises a first access means to access the memory cell array by a column direction and a second access means to access the memory cell array by a row direction. In this manner data is read from a magnetoresistive memory module in both row and column directions.
    Type: Application
    Filed: July 14, 2005
    Publication date: November 10, 2005
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Koichi Fujisaki, Kentaro Nakajima, Takeshi Chujoh, Yasuhiro Taniguchi
  • Publication number: 20050245045
    Abstract: A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transistor having a gate insulating film formed over a second element forming region of the main surface of the semiconductor substrate and made thinner than the gate insulating film of the first field effect transistor.
    Type: Application
    Filed: July 12, 2005
    Publication date: November 3, 2005
    Inventors: Shoji Shukuri, Norio Suzuki, Yasuhiro Taniguchi
  • Patent number: 6934196
    Abstract: A memory cell module comprises a memory cell array formed by memory cells of M columns×N rows. Each memory cell includes a magnetoresistive element or a magnetresistive element with a semiconductor element. A memory module comprises a first access means to access the memory cell array by a column direction and a second access means to access the memory cell array by a row direction. In this manner, data is read from a magnetoresistive memory module in both row and column directions.
    Type: Grant
    Filed: July 23, 2002
    Date of Patent: August 23, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Fujisaki, Kentaro Nakajima, Takeshi Chujoh, Yasuhiro Taniguchi
  • Patent number: 6908837
    Abstract: A method of manufacturing a semiconductor integrated circuit device includes the steps of depositing a first insulating film over a first conductive layer, patterning the first insulating film by using a resist film as a mask to form a cap film, and removing the resist film. After which, a gate electrode of a MISFET is formed by etching the first conductive layer using the cap film as a mask. A second insulating film is deposited over the gate electrode and the cap film and a side wall spacer formed on side surfaces of the gate electrode by etching the second insulating film. After which, a salicide layer is selectively formed on the gate electrode. The cap film is removed by over-etching the first insulating film to etch the cap film.
    Type: Grant
    Filed: September 23, 2002
    Date of Patent: June 21, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Yasuhiro Taniguchi, Shoji Shukuri, Kenichi Kuroda, Shuji Ikeda, Takashi Hashimoto
  • Patent number: 6842376
    Abstract: A method for settling threshold voltages of word lines on a predetermined level in an erasing processing of a non-volatile semiconductor memory device so as to speed up the erasing processing. A word latch circuit is provided for each word line and the threshold voltage of each memory cell is managed for each word line in a selected memory block. Each word latch circuit is shared by a plurality of word lines so as to reduce the required chip area. A rewriting voltage is set for each finished non-volatile memory and the voltage information is stored in the boot area of the non-volatile memory, so that the voltage is recognized by the system each time the system is powered.
    Type: Grant
    Filed: August 12, 2003
    Date of Patent: January 11, 2005
    Assignees: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Nozomu Matsuzaki, Kazuyoshi Shiba, Yasuhiro Taniguchi, Toshihiro Tanaka, Yutaka Shinagawa
  • Publication number: 20040141063
    Abstract: A first mirror and a second mirror are disposed in such a manner that their reflective surfaces are parallel and face toward each other. A mark is drawn between the first mirror and the second mirror. An image of the reflections of the mark in the first mirror and the second mirror is captured with a camera. Calibration of the camera system is performed based on the image.
    Type: Application
    Filed: November 12, 2003
    Publication date: July 22, 2004
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kenichi Maeda, Yasuhiro Taniguchi, Susumu Kubota, Hiroaki Nakai
  • Patent number: 6711061
    Abstract: A method for settling threshold voltages of word lines on a predetermined level in an erasing processing of a non-volatile semiconductor memory device so as to speed up the erasing processing. A word latch circuit is provided for each word line and the threshold voltage of each memory cell is managed for each word line in a selected memory block. Each word latch circuit is shared by a plurality of word lines so as to reduce the required chip area. A rewriting voltage is set for each finished non-volatile memory and the voltage information is stored in the boot area of the non-volatile memory, so that the voltage is recognized by the system each time the system is powered.
    Type: Grant
    Filed: August 20, 2002
    Date of Patent: March 23, 2004
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Nozomu Matsuzaki, Kazuyoshi Shiba, Yasuhiro Taniguchi, Toshihiro Tanaka, Yutaka Shinagawa
  • Publication number: 20040047223
    Abstract: A method for settling threshold voltages of word lines on a predetermined level in an erasing processing of a non-volatile semiconductor memory device so as to speed up the erasing processing. A word latch circuit is provided for each word line and the threshold voltage of each memory cell is managed for each word line in a selected memory block. Each word latch circuit is shared by a plurality of word lines so as to reduce the required chip area. A rewriting voltage is set for each finished non-volatile memory and the voltage information is stored in the boot area of the non-volatile memory, so that the voltage is recognized by the system each time the system is powered.
    Type: Application
    Filed: August 12, 2003
    Publication date: March 11, 2004
    Applicants: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Nozomu Matsuzaki, Kazuyoshi Shiba, Yasuhiro Taniguchi, Toshihiro Tanaka, Yutaka Shinagawa
  • Publication number: 20040031988
    Abstract: A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transistor having a gate insulating film formed over a second element forming region of the main surface of the semiconductor substrate and made thinner than the gate insulating film of the first field effect transistor.
    Type: Application
    Filed: August 7, 2003
    Publication date: February 19, 2004
    Inventors: Shoji Shukuri, Norio Suzuki, Yasuhiro Taniguchi
  • Patent number: 6646313
    Abstract: A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transistor having a gate insulating film formed over a second element forming region of the main surface of the semiconductor substrate and made thinner than the gate insulating film of the first field effect transistor.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: November 11, 2003
    Assignee: Hitachi, Ltd
    Inventors: Shoji Shukuri, Norio Suzuki, Yasuhiro Taniguchi
  • Patent number: 6617632
    Abstract: A parallel connection-type nonvolatile memory semiconductor device comprises a plurality of memory cells disposed on a semiconductor substrate in matrix form, each including a gate insulating film, a floating gate electrode, an interlayer film and a control gate electrode successively formed so as to cover a channel region on a main surface of the semiconductor substrate, of a first conductivity type; a second conductivity type source and drain regions formed on the semiconductor substrate on both sides opposite to each other, of the floating gate electrode so as to interpose a channel region located under the floating gate electrode therebetween; a first semiconductor region which is adjacent to the drain region and formed by introducing a second conductivity type impurity in the direction of the channel region placed under the floating gate electrode from an end on the drain side, of the floating gate electrode, and which is substantially lower than the drain region in impurity concentration; and a punch-th
    Type: Grant
    Filed: December 7, 2001
    Date of Patent: September 9, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Yasuhiro Taniguchi, Kazuyoshi Shiba, Nozomu Matsuzaki, Hidenori Takada, Hitoshi Kume, Shoji Shukuri
  • Publication number: 20030151109
    Abstract: A MISFET capable of a high speed operation includes a metal silicide layer in a high concentration region aligned with a gate side wall layer on a self-alignment basis. A MISFET which can be driven at a high voltage includes an LDD portion having a width greater than the width of the side wall layer, a high concentration region in contact with the LDD portion and a metal silicide layer in the high concentration region.
    Type: Application
    Filed: September 23, 2002
    Publication date: August 14, 2003
    Inventors: Yasuhiro Taniguchi, Shoji Shukuri, Kenichi Kuroda, Shuji Ikeda, Takashi Hashimoto
  • Patent number: 6576512
    Abstract: A MISFET capable of a high speed operation includes a metal silicide layer in a high concentration region aligned with a gate side wall layer on a self-alignment basis. A MISFET which can be driven at a high voltage includes an LDD portion having a width greater than the width of the side wall layer, a high concentration region in contact with the LDD portion and a metal silicide layer in the high concentration region.
    Type: Grant
    Filed: September 23, 2002
    Date of Patent: June 10, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Yasuhiro Taniguchi, Shoji Shukuri, Kenichi Kuroda, Shuji Ikeda, Takashi Hashimoto