Abstract: With respect to design regarding a bus cycle, it has been necessary to consider a data conflict, if an output disable time of a device is long. A bus controlling unit is installed in a processor. In the bus controlling unit, parameters regarding output disable times of external devices such as a first device are utilized. When a device with a long output disable time is read in a bus cycle, an idle state is forcibly inserted before a following bus cycle activation to avoid a data conflict.

Abstract: A data processing apparatus uses a stored-program method to execute an operation instructed by an instruction word that includes a register designation code as an operand. A plurality of work registers are identifiable by register numbers, each of a typical number of bits. A correspondence table holds at least one of the register numbers in a state corresponding to register designation codes. The codes are stored in a readable condition, and have fewer bits than the register numbers. The data processing apparatus refers to the correspondence table when executing the operation.

Abstract: When a process branches to an interrupt processing routine, the value stored in a return address holding register ERP is transferred to a register R2 via the initial MOVS instruction. Upon the next SETPR instruction (an acceptable interrupt level setting instruction), an EA (interrupt allowance) flag is automatically set at 1, whereby multiple interrupts are allowed. For process returning, the value saved in the register R2 is transferred to the ERP register via a data transfer instruction MOVS, upon which the EA flag is automatically set at 0 to thereby inhibit receipt of interrupt requests. Upon execution of the last RETI instruction, receipt of interrupt requests is again allowed.

Abstract: With respect to design regarding a bus cycle, it has been necessary to consider a data conflict, if an output disable time of a device is long. A bus controlling unit is installed in a processor. In the bus controlling unit, parameters regarding output disable times of external devices such as a first device are utilised. When a device with a long output disable time is read in a bus cycle, an idle state is forcibly inserted before a following bus cycle activation to avoid a data conflict.

Abstract: To simplify the process relative to an instruction array including an instruction for a process with flag handling executed by a compiler when converting a high-level program into in a format executable by a program executing apparatus, a number of operating circuits, namely, an ALU circuit and a AND operation circuit, are provided to operate in parallel to handle different flags in a flag group based on the results of respective operations. A value comparison instruction and a bit test instruction are converted into common operation process instructions, and branch instructions, dependent on the result of the execution of the operation process instructions, are prepared so as to detect different flag patterns. The common use of an operation instruction for a number of flag-handling instructions simplifies a compiler judgement.

Abstract: An instruction decoder decodes an instruction code, whereupon immediate data, if included, is searched to see whether it is encoded or not. After decoding, an operation code in the instruction code is informed to the execution unit. If the instruction code includes immediate data, the data is transmitted to a data decoder to be decoded according to a given rule. The decoded data is transmitted to the execution unit. Because the immediate data is reduced in size through encoding, the number of times instructions are fetched is accordingly reduced, which resultantly increases processing efficiency. Since an entire instruction code is also reduced in size, a wider variety of operations are instructed using the same instruction code format.

Abstract: A clock control method is proposed, in which malfunctions caused by clock skews are decreased when the same high-speed clock is used inside and outside an IC. An original clock is input via CKIN, with the return path of an output buffer connected to an input buffer in an input/output buffer. The clock, once output via the output buffer, returns to the IC as a reentry clock. The selected reentry clock or original clock are used in the IC. The clock appearing at SYSCK is used in an external circuit. By using the reentry clock in the IC, the clock skew corresponding to the delay of the output buffer can be decreased.

Abstract: Disclosed is a program execution device capable of carrying out high-speed computation with a low amount of hardware and small program size, while permitting future expansion of the range of functions. General-purpose registers R0˜R4 are virtual registers and a specific computation is related to read/write processing to and from each of these registers R0˜R4. When instruction decoder 3 has decoded an instruction, if it has been determined that the instruction is a data transfer instruction denoting access to any one of the general-purpose registers R0˜4, the computation related to the register to be accessed is carried out. A expanded range of computation types can be related to different general-purpose registers.

Abstract: A group of registers 26 consists of a plurality of general-purpose registers R0, R1, . . . . A flag is provided for each of these general-purpose registers. When data to be written to, for instance, general-purpose register R0 is zero, the register flag is set in conjunction with the data writing. Thereafter, it is possible to determine with a conditional branching instruction if the general-purpose register R0 data is zero by looking at the flag, and there is no need to read out data and perform a computation.

Abstract: A processor that executes an instruction stream having at least one compressed register field allows for smaller programs and greater processing speed. The instructions have at least one n-bit register number field and at least one m-bit register code field, where n is less than m. The n-bit register number field is capable of designating any register in a set of working registers. The m-bit register code field is capable of designating any register of a subset of the working registers. The m-bit register code may designate a source or destination register of the current instruction, a source or destination register of the last instruction, or a destination register of the second to last instruction. An instruction fetch section of the processor fetches the instruction words from memory.

Abstract: An instruction fetcher reads out instructions and data from a memory. The instructions and data are decoded by an instruction decoder. When a data transfer instruction is fed to an input register in a register section, a second execution unit starts an execution, the execution result being then stored in an output register. If any unprocessed data remains in the input or output register, the subsequent data processing is suspended. Input and output register sets and execution sub-units may be provided such that any of these components can be selected depending on the necessary process. Since a given execution is executed by the data transfer instruction, the data can be processed at high speed through a simplified program. Since no specific and additional computation instruction is required, the expandability can be improved.

Abstract: A processor uses a special instruction set to enhance exception handling, such as interrupt handling. The processor uses a pipeline comprising five separate stages of fetch, decode, execute, memory access and register write. For each operation executed by the processor, the operation has an operation initiation instruction and an operation result fetch instruction, each of which has multiple stages. The operation result fetch instruction awaits the completion of the operation initiation instruction. While waiting, the operation result fetch instruction is suspended, preferably before any hardware resource is changed, and if necessary canceled to accommodate an exception handling signal. Since the hardware resource is changed at the "execute" stage of the operation, the operation result fetch instruction is suspended at the "decode" stage. Upon receiving the exception handling signal, the operation result fetch instruction may be canceled and the processor is free to process the exception handling.

Abstract: A parallel computer system includes a plurality of processing elements each comprising a network control unit. The network control unit of the processing element has ports to north, east, west and south, and row directional communication lines and column directional communication lines are connected to each port forming a taurus mesh network. Each processing element operates in two communication control modes, in a bi-directional communication mode or in a unidirectional communication mode. In the bi-directional communication mode, the network control unit permits eastward and westward transmission of data through the row directional communication lines and northward and southward transmission of data through the column directional communication lines.

Abstract: A second execution unit such as a coprocessor incorporated into a processor is connected such that the direction of its processing flow is opposite to that of the main pipeline processing flow, and executes high-speed multiplication operations and specific operations. Conventionally, the second execution unit has been provided in the same direction as a first execution unit. With this prior art arrangement, the second execution unit is initiated at an early stage of pipeline processing. With the arrangement of this invention, the second execution unit is initiated at a later stage, giving sufficient time before all the operation data are prepared. Thus, it is unnecessary for the apparatus to start subsequent processing until all operation data become available, thereby enhancing processing performance.

Abstract: A parallel computer includes a plurality of processors arranged in a taurus mesh network, with each processor having a local memory, and a plurality of secondary storage units. The network is coupled to a host computer via a host interface. Interleave system information corresponding to the size of portions of a file to be divided and stored in the plurality of secondary storage units is also stored in the local memory of a processor. When the processor accesses the file, the interleave system information of the file in the processor local memory is referenced by the processor and the processor outputs a file transfer request in accordance with the interleave system information.

Abstract: An instruction decoder decodes an instruction code, whereupon immediate data, if included, is searched to see whether it is encoded or not. After decoding, an operation code in the instruction code is informed to the execution unit. If the instruction code includes immediate data, the data is transmitted to a data decoder to be decoded according to a given rule. The decoded data is transmitted to the execution unit. Because the immediate data is reduced in size through encoding, the number of times instructions are fetched is accordingly reduced, which resultantly increases processing efficiency. Since an entire instruction code is also reduced in size, a wider variety of operations are instructed using the same instruction code format.

Abstract: A parallel computer system includes a plurality of processing elements each comprising a network control unit. The network control unit of the processing element has ports to north, east, west and south, and row directional communication lines and column directional communication lines are connected to each port forming a taurus mesh network. Each processing element operates in two communication control modes, in a bi-directional communication mode or in a unidirectional communication mode. In the bi-directional communication mode, the network control unit permits eastward and westward transmission of data through the row directional communication lines and northward and southward transmission of data through the column directional communication lines.