Patents by Inventor Yasumichi Hatanaka

Yasumichi Hatanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10720368
    Abstract: A semiconductor device includes: an insulating substrate having an upper surface on which a semiconductor element is mounted; a base plate joined to a lower surface of the insulating substrate; a case member that surrounds the insulating substrate and that is in contact with a surface of the base plate to which the insulating substrate is joined; a sealing resin provided in a region surrounded by the base plate and the case member; a cover member facing a surface of the sealing resin and fixed to the case member; and a holding plate, a lower surface of the holding plate and a portion of a side surface of the holding plate being in close contact with the surface of the sealing resin, an upper surface of the holding plate being fixed to and protruding from a surface of the cover member facing the surface of the sealing resin.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: July 21, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hiroyuki Harada, Kozo Harada, Yasumichi Hatanaka, Takashi Nishimura, Masaki Taya
  • Publication number: 20190371686
    Abstract: A semiconductor device includes: an insulating substrate having an upper surface on which a semiconductor element is mounted; a base plate joined to a lower surface of the insulating substrate; a case member that surrounds the insulating substrate and that is in contact with a surface of the base plate to which the insulating substrate is joined; a sealing resin provided in a region surrounded by the base plate and the case member; a cover member facing a surface of the sealing resin and fixed to the case member; and a holding plate, a lower surface of the holding plate and a portion of a side surface of the holding plate being in close contact with the surface of the sealing resin, an upper surface of the holding plate being fixed to and protruding from a surface of the cover member facing the surface of the sealing resin.
    Type: Application
    Filed: December 14, 2016
    Publication date: December 5, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Hiroyuki HARADA, Kozo HARADA, Yasumichi HATANAKA, Takashi NISHIMURA, Masaki TAYA
  • Patent number: 10468315
    Abstract: The power module includes: an insulating substrate having an upper surface on which a semiconductor element is mounted; a base plate joined to a lower surface of the insulating substrate; a case member surrounding the insulating substrate and adhered to the base plate; a sealing resin provided in a region surrounded by the base plate and the case member, so as to seal the insulating substrate; and a holding plate projecting from an inner wall of the case member to above an outer peripheral portion of the insulating substrate, the holding plate being fixed to the inner wall, the holding plate being in contact with the sealing resin.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: November 5, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kozo Harada, Hiroyuki Harada, Yasumichi Hatanaka, Takashi Nishimura, Masaki Taya
  • Patent number: 10461045
    Abstract: A power semiconductor device including an insulating substrate having a metal layer formed on an upper surface thereof, a semiconductor element and a main electrode bonded to the metal layer, a metal wire connecting the metal layer with the semiconductor element, a metal member bonded to a lower surface side of the insulating substrate, a case member surrounding the insulating substrate and being in contact with a surface of the metal member bonded to the insulating substrate, and a sealing resin which fills a region surrounded by the metal member and the case member and has a resin strength of 0.12 MPa or higher at room temperature, a microcrystallization temperature of ?55° C. or lower, and a needle penetration of 30 to 50 after storage at 175° C. for 1000 hours and seals the insulating substrate, the metal layer, the semiconductor element, the metal wire, and the main electrode.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: October 29, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yasumichi Hatanaka, Kozo Harada, Hiroyuki Harada, Takashi Nishimura, Masayuki Mafune, Koji Yamada
  • Publication number: 20190267331
    Abstract: A power semiconductor device including an insulating substrate having a metal layer formed on an upper surface thereof, a semiconductor element and a main electrode bonded to the metal layer, a metal wire connecting the metal layer with the semiconductor element, a metal member bonded to a lower surface side of the insulating substrate, a case member surrounding the insulating substrate and being in contact with a surface of the metal member bonded to the insulating substrate, and a sealing resin which fills a region surrounded by the metal member and the case member and has a resin strength of 0.12 MPa or higher at room temperature, a microcrystallization temperature of ?55° C. or lower, and a needle penetration of 30 to 50 after storage at 175° C. for 1000 hours and seals the insulating substrate, the metal layer, the semiconductor element, the metal wire, and the main electrode.
    Type: Application
    Filed: July 1, 2016
    Publication date: August 29, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yasumichi HATANAKA, Kozo Harada, Hiroyuki Harada, Takashi Nishimura, Masayuki Mafune, Koji Yamada
  • Patent number: 10170433
    Abstract: An insulated circuit board includes an insulated substrate, a first electrode, and a second electrode. A thin portion is formed in a corner portion, the corner portion being a region occupying, with regard to directions along outer edges from a vertex of at least one of the first and second electrodes in plan view, a portion of a length of the outer edges, and the thin portion has a thickness smaller than that of a region other than the thin portion. The thin portion in at least one of the first and second electrodes has a planar shape surrounded by first and second sides orthogonal to each other as portions of the outer edges from the vertex, and a curved portion away from the vertex of the first and second sides.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: January 1, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shinnosuke Soda, Yohei Omoto, Komei Hayashi, Shinji Tsukamoto, Yasumichi Hatanaka
  • Publication number: 20180323120
    Abstract: The power module includes: an insulating substrate having an upper surface on which a semiconductor element is mounted; a base plate joined to a lower surface of the insulating substrate; a case member surrounding the insulating substrate and adhered to the base plate; a sealing resin provided in a region surrounded by the base plate and the case member, so as to seal the insulating substrate; and a holding plate projecting from an inner wall of the case member to above an outer peripheral portion of the insulating substrate, the holding plate being fixed to the inner wall, the holding plate being in contact with the sealing resin.
    Type: Application
    Filed: November 1, 2016
    Publication date: November 8, 2018
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kozo HARADA, Hiroyuki HARADA, Yasumichi HATANAKA, Takashi NISHIMURA, Masaki TAYA
  • Publication number: 20170338189
    Abstract: An insulated circuit board includes an insulated substrate, a first electrode, and a second electrode. A thin portion is formed in a corner portion, the corner portion being a region occupying, with regard to directions along outer edges from a vertex of at least one of the first and second electrodes in plan view, a portion of a length of the outer edges, and the thin portion has a thickness smaller than that of a region other than the thin portion. The thin portion in at least one of the first and second electrodes has a planar shape surrounded by first and second sides orthogonal to each other as portions of the outer edges from the vertex, and a curved portion away from the vertex of the first and second sides.
    Type: Application
    Filed: October 13, 2015
    Publication date: November 23, 2017
    Applicant: Mitsubishi Electric Corporation
    Inventors: Shinnosuke SODA, Yohei OMOTO, Komei HAYASHI, Shinji TSUKAMOTO, Yasumichi HATANAKA
  • Publication number: 20130312810
    Abstract: In a solar battery module including a plurality of solar battery elements each including electrodes that are electrically connected by an electrically conductive wiring member, the electrode and the wiring member are welded by solder on the electrode, resin is arranged while covering at least a side surface of a solder-bonded portion between the solder and the electrode, and a wetted height of the resin on a side surface of the wiring member is lower than the top of wiring member, so that welding by the solder can be reinforced and the bonding reliability can be improved.
    Type: Application
    Filed: April 5, 2012
    Publication date: November 28, 2013
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Tsuneo Hamaguchi, Yoshimi Yabugaki, Shinsuke Miyamoto, Yasumichi Hatanaka
  • Patent number: 7951699
    Abstract: A method of manufacturing a semiconductor device includes a first step of forming solder film on metal posts of a mother chip, a second step of forming solder balls after the first step by printing a solder paste on the mother chip and heating the mother chip so that the solder paste is ref lowed, a third step of bonding the metal posts of the mother chip and metal posts of a daughter chip to each other in a thermocompression bonding manner by means of the solder film after the second step, and a fourth step of flip-chip-connecting the mother chip on a circuit substrate by using the solder balls. In the second step, the mother chip is heated in a nitrogen atmosphere in which the oxygen concentration is 500 ppm or less.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: May 31, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Toshihiro Iwasaki, Shiori Idaka, Yasumichi Hatanaka
  • Publication number: 20070141750
    Abstract: A method of manufacturing a semiconductor device includes a first step of forming solder film on metal posts of a mother chip, a second step of forming solder balls after the first step by printing a solder paste on the mother chip and heating the mother chip so that the solder paste is ref lowed, a third step of bonding the metal posts of the mother chip and metal posts of a daughter chip to each other in a thermocompression bonding manner by means of the solder film after the second step, and a fourth step of flip-chip-connecting the mother chip on a circuit substrate by using the solder balls. In the second step, the mother chip is heated in a nitrogen atmosphere in which the oxygen concentration is 500 ppm or less.
    Type: Application
    Filed: December 12, 2006
    Publication date: June 21, 2007
    Inventors: Toshihiro Iwasaki, Shiori Idaka, Yasumichi Hatanaka
  • Patent number: 7078330
    Abstract: A metal electrode is formed on a substrate. The metal electrode includes a first layer, a second layer, and a third layer lying, from an outermost surface of the metal electrode toward the substrate, in this order. The first layer contains tin as a principal constituent and the second layer contains a metallic element which produces an eutectic reaction with tin, wherein the melting point of the first layer is higher than the melting point of the second layer. The third layer is an underlying metallic layer for the first and second layers.
    Type: Grant
    Filed: March 3, 2004
    Date of Patent: July 18, 2006
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Akira Maeda, Takeyuki Maegawa, Shigeru Matsuno, Takuo Ozawa, Takanori Sone, Shoji Miyashita, Yasumichi Hatanaka, Masato Koyama, Takahiro Nagamine, Susumu Arai
  • Publication number: 20040175917
    Abstract: A metal electrode of the invention is formed on a substrate. The metal electrode includes a first layer, a second layer and a third layer lying from an outermost surface of the metal electrode toward the substrate in this order. The first layer contains tin as a principal constituent and the second layer contains a metallic element which produces an eutectic reaction with tin, wherein the melting point of the first layer is higher than that of the second layer. The third layer is formed as an underlying metallic layer for the first and second layers.
    Type: Application
    Filed: March 3, 2004
    Publication date: September 9, 2004
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Akira Maeda, Takeyuki Maegawa, Shigeru Matsuno, Takuo Ozawa, Takanori Sone, Shoji Miyashita, Yasumichi Hatanaka, Masato Koyama, Takahiro Nagamine, Susumu Arai
  • Patent number: 6777814
    Abstract: A semiconductor device includes a semiconductor chip, and a circuit substrate disposed such that the circuit substrate faces the semiconductor chip and is electrically connected to the semiconductor chip through a connection conductor. A pad electrode and a terminal electrode are formed on a surface of the semiconductor chip and a surface of the circuit substrate, respectively. The connection conductor is connected between the pad electrode and the terminal electrode. The surface of the semiconductor and the surface of the circuit substrate face each other. A conductive dummy pattern is formed on the facing surface of the semiconductor chip or the circuit substrate. A space between the facing surfaces is filled with nonconductive resin. With this arrangement, it is possible to make uniform the temperature distribution between the facing surfaces, thereby making the temperature and the viscosity of the nonconductive resin uniform to reduce attenuation of ultrasonic waves.
    Type: Grant
    Filed: June 14, 2002
    Date of Patent: August 17, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Toshihiro Iwasaki, Michitaka Kimura, Keiichiro Wakamiya, Yasumichi Hatanaka
  • Patent number: 6756686
    Abstract: A semiconductor device includes a first substrate, a second substrate, a plurality of conductors, and supporting members. The first substrate has a plurality of electrode portions disposed on one side thereof. The second substrate has a plurality of electrode portions disposed on one side thereof. The conductors are for connecting the plurality of electrode portions of the first substrate to the plurality of electrode portions of the second substrate. The supporting members supporting the first substrate and the second substrate are disposed on a location where resonance caused by ultrasonic oscillation externally supplied is restrained in the state where the first substrate is connected to the second substrate. The supporting members prevent irregular oscillation and resonance caused by the ultrasonic oscillation.
    Type: Grant
    Filed: August 21, 2002
    Date of Patent: June 29, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Toshihiro Iwasaki, Keiichiro Wakamiya, Michitaka Kimura, Yasumichi Hatanaka
  • Patent number: 6677677
    Abstract: The semiconductor device has a flip chip structure. The chip is electrically connected to the chip mounting member via function bumps provided on the chip. Dummy bumps acting against a local bending force of the chip are interposed between the chip and the chip mounting member.
    Type: Grant
    Filed: March 27, 2002
    Date of Patent: January 13, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Michitaka Kimura, Toshihiro Iwasaki, Yasumichi Hatanaka, Keiichiro Wakamiya
  • Publication number: 20030111742
    Abstract: The present invention comprises: a semiconductor chip; a circuit substrate disposed such that the circuit substrate faces the semiconductor chip and is electrically connected to the semiconductor chip through a connection conductor; a pad electrode and a terminal electrode formed on a surface of the semiconductor chip and a surface of the circuit substrate, respectively, and having the connection conductor connected thereto, the surface of the semiconductor and the surface of the circuit substrate facing each other; nonconductive resin formed such that the nonconductive resin fills a space between the facing surfaces; and a conductive dummy pattern formed on the facing surface of the semiconductor chip or the circuit substrate, the conductive dummy pattern having a predetermined shape.
    Type: Application
    Filed: June 14, 2002
    Publication date: June 19, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshihiro Iwasaki, Michitaka Kimura, Keiichiro Wakamiya, Yasumichi Hatanaka
  • Publication number: 20030060035
    Abstract: The semiconductor device has a flip chip structure. The chip is electrically connected to the chip mounting member via function bumps provided on the chip. Dummy bumps acting against a local bending force of the chip are interposed between the chip and the chip mounting member.
    Type: Application
    Filed: March 27, 2002
    Publication date: March 27, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Michitaka Kimura, Toshihiro Iwasaki, Yasumichi Hatanaka, Keiichiro Wakamiya
  • Publication number: 20030057537
    Abstract: A semiconductor device includes a first substrate, a second substrate, a plurality of conductors, and supporting members. The first substrate has a plurality of electrode portions disposed on one side thereof. The second substrate has a plurality of electrode portions disposed on one side thereof. The conductors are for connecting the plurality of electrode portions of the first substrate to the plurality of electrode portions of the second substrate. The supporting members supporting the first substrate and the second substrate are disposed on a location where resonance caused by ultrasonic oscillation externally supplied is restrained in the state where the first substrate is connected to the second substrate. The supporting members prevent irregular oscillation and resonance caused by the ultrasonic oscillation.
    Type: Application
    Filed: August 21, 2002
    Publication date: March 27, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshihiro Iwasaki, Keiichiro Wakamiya, Michitaka Kimura, Yasumichi Hatanaka
  • Publication number: 20030057569
    Abstract: A semiconductor device is used which is provided with a semiconductor chip having Au bumps on its surface and a chip-mounting substrate having external electrode lands on its chip-mounting face while having external electrode pads on its external connection face and constituted by bonding Au bumps on the semiconductor chip to internal electrode pads on the chip-mounting substrate while turning the semiconductor chip upside down, in which external electrode lands are arranged in areas corresponding to arrangement areas of internal electrode pads at the both sides of the chip-mounting substrate.
    Type: Application
    Filed: March 6, 2002
    Publication date: March 27, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Keiichiro Wakamiya, Toshihiro Iwasaki, Michitaka Kimura, Yasumichi Hatanaka