Abstract: A method for fabricating a semiconductor device according to the present invention is a method for fabricating a semiconductor device including a substrate layer including a plurality of first regions each having an active region and a plurality of second regions each being provided between adjacent ones of the first region. The fabrication method includes an isolation insulation film formation step of forming an isolation insulation film in each of the second regions so that a surface of the isolation insulation film becomes at the same height as that of a surface of a gate oxide film covering the active region, a peeling layer formation step of forming a peeling layer by ion-implanting hydrogen into the substrate layer after the isolation insulation film formation step, and a separation step of separating part of the substrate layer along the peeling layer.

Abstract: In fabricating a semiconductor device, an element forming surface formation step of forming a plurality of element forming surfaces of different heights on a semiconductor layer to have different levels, a semiconductor element formation step of forming a plurality of semiconductor elements and, one in each of a corresponding number of regions of the semiconductor layer, each region including an associated one of the plurality of element forming surfaces, a level-difference compensation insulating film formation step of forming a level-difference compensation insulating film on the semiconductor layer to cover the semiconductor elements and have a surface with different levels along the element forming surfaces, a release layer formation step of forming a release layer in the semiconductor layer by ion-implanting a peeling material through the level-difference compensation insulating film into the semiconductor layer, and a separation step of separating part of the semiconductor layer along the release layer

Abstract: The present invention provides a semiconductor device wherein the area of a peripheral circuit region with respect to a pixel region is reduced, and provides a manufacturing method of the semiconductor device. A semiconductor device according to the present invention is characterized by having a pixel region 1, peripheral circuit regions 2a to 2c arranged in at least a part of the periphery of the pixel region, and a wiring formed in the peripheral circuit region, and by having a wiring multilayered with two or more layers. At least one layer of the multilyered wiring is formed from a low resistance material. Transistors are formed in the peripheral circuit region, and the multilayer wiring with two or more layers is formed on the upper side of the transistors.

Abstract: A method for fabricating a semiconductor device according to the present invention is a method for fabricating a semiconductor device including a substrate layer including a plurality of first regions each having an active region and a plurality of second regions each being provided between adjacent ones of the first region. The fabrication method includes an isolation insulation film formation step of forming an isolation insulation film in each of the second regions so that a surface of the isolation insulation film becomes at the same height as that of a surface of a gate oxide film covering the active region, a peeling layer formation step of forming a peeling layer by ion-implanting hydrogen into the substrate layer after the isolation insulation film formation step, and a separation step of separating part of the substrate layer along the peeling layer.

Abstract: A method for manufacturing a semiconductor substrate comprises the steps of: forming a gate oxide film as an insulating layer on the surface of a semiconductor substrate; implanting boron ions for inhibiting the migration of a peeling substance in the semiconductor substrate to form an anti-diffusion layer in the semiconductor substrate; activating boron in the anti-diffusion layer by heat treatment; implanting hydrogen ions into the semiconductor substrate to form a peel layer in part of the semiconductor substrate at a side of the anti-diffusion layer opposite to the gate oxide film; bonding a glass substrate to the surface of the semiconductor substrate where the gate oxide film has been formed; and heat-treating the semiconductor substrate to separate part of the semiconductor substrate along the peel layer.

Abstract: The present invention provides a semiconductor substrate, which comprises a singlecrystalline Si substrate which includes an active layer having a channel region, a source region, and a drain region, the singlecrystalline Si substrate including at least a part of a device structure not containing a well-structure or a channel stop region; a gate insulating film formed on the singlecrystalline Si substrate; a gate electrode formed on the gate insulating film; a LOCOS oxide film whose thickness is more than a thickness of the gate insulating film, the LOCOS oxide film being formed on the singlecrystalline Si substrate by surrounding the active layer; and an insulating film formed over the gate electrode and the LOCOS oxide film.

Abstract: A thin film transistor of the present invention is provided with (i) a plurality of divided channel regions formed under a gate electrode, and (ii) divided source regions and divided drain regions between which each of the divided channel regions is sandwiched, the divided source regions being connected with one another, and the divided drain regions being connected with one another. Here, the divided channel regions are so arranged that a spacing between the divided channel regions is smaller than a channel divided width which is a width of one divided channel region, the channel divided width is not more than 50 ?m, and the spacing is not less than 3 ?m. With this arrangement, it is possible to provide a thin film transistor capable of obtaining reliability with reducing the variation in threshold voltage by reducing the self-heating at the channel regions, as well as capable of reducing the increase of a layout area.

Abstract: The object of the invention is to provide an active matrix liquid crystal display device having improved brightness and higher contrast, and the method for manufacturing the same. An active matrix liquid crystal display device has on the upper side and the lower side of the switching element, arranged in matrix, a lower shading layer and an upper shading layer. Either the lower shading layer or the upper shading layer is, or both the lower and upper shading layers are, formed to have a convex shape and a sloped portion protruding toward the switching element.

Abstract: The present invention provides a semiconductor device wherein the area of a peripheral circuit region with respect to a pixel region is reduced, and provides a manufacturing method of the semiconductor device. A semiconductor device according to the present invention is characterized by having a pixel region 1, peripheral circuit regions 2a to 2c arranged in at least a part of the periphery of the pixel region, and a wiring formed in the peripheral circuit region, and by having a wiring multilayered with two or more layers. At least one layer of the multilyered wiring is formed from a low resistance material. Transistors are formed in the peripheral circuit region, and the multilayer wiring with two or more layers is formed on the upper side of the transistors.

Abstract: There is provided a semiconductor device capable of reducing dispersion in electrical characteristics, preventing occurrence of bridge shortcircuit in a silicide process and operating at high operating speed and method for fabricating the same. In a SOI substrate obtained by forming an insulating layer 2 and a SOI layer 3 on a silicon substrate 1, there are formed a channel region 19, an LDD region 15a and source and drain junction regions 17 and 18 in the SOI layer 3. A gate electrode 14 whose both side walls have a shape roughly perpendicular to the SOI substrate is formed via a gate insulating film on the channel region 19. An oxide film spacer 16 is formed on the LDD region 15a on both side wall sides of the gate electrode 14.

Abstract: A thin film transistor of the present invention is provided with (i) a plurality of divided channel regions formed under a gate electrode, and (ii) divided source regions and divided drain regions between which each of the divided channel regions is sandwiched, the divided source regions being connected with one another, and the divided drain regions being connected with one another. Here, the divided channel regions are so arranged that a spacing between the divided channel regions is smaller than a channel divided width which is a width of one divided channel region, the channel divided width is not more than 50 &mgr;m, and the spacing is not less than 3 &mgr;m. With this arrangement, it is possible to provide a thin film transistor capable of obtaining reliability with reducing the variation in threshold voltage by reducing the self-heating at the channel regions, as well as capable of reducing the increase of a layout area.

Abstract: There is provided a semiconductor manufacturing method capable of sufficiently reducing catalytic element in a crystalline silicon film and also increasing the area of the crystalline silicon film to be left on the substrate. A catalytic element for accelerating the crystallization is introduced into an amorphous silicon film on a substrate, and a first heat treatment is performed to crystallize the amorphous silicon film into a crystalline silicon film. A mask layer is provided on the surface of the crystalline silicon film, the mask layer having an opening passing thicknesswise through the mask layer. Further thereon, a sacrifice film is formed so as to continuously cover the surface of the mask layer and an opening-correspondent portion of the crystalline silicon film. A getter element for gettering the catalytic element is introduced into the sacrifice film and the opening-correspondent portion of the crystalline silicon film.

Abstract: In a method of producing a semiconductor device, an a-Si film is crystallized using nickel to form a CGS film. Then, an a-Si film containing phosphorus is directly formed on the whole surface of the CGS film, and then the CGS film and the a-Si film are subjected to heat treatment to thereby getter the nickel from the CGS film the a-Si film. The a-Si film containing nickel and phosphorus is removed. Then, using the thus obtained CGS film for an active region, a thin-film transistor is formed.

Abstract: There is provided a quantum thin line producing method capable of forming a quantum thin line that has good surface flatness of silicon even after formation of quantum thin line and a complete electron confining region with good controllability as well as a semiconductor device employing the quantum thin line. A region of a nitride film 3 which covers a semiconductor substrate 1 on which a stepped portion 2 is formed is etched back with masking, consequently exposing an upper portion of a semiconductor substrate 1. Next, an oxide film 5 is formed by oxidizing the exposed portion of the upper portion of the semiconductor substrate 1, and a linear protruding portion 6 is formed on the semiconductor substrate along a side surface of the nitride film 3. Next, the oxide film 5 on the protruding portion 6 is partially etched to expose a tip of the protruding portion 6. Next, a thin line portion 7 is made to epitaxially grow on the exposed portion at the tip of the protruding portion 6.

Abstract: A nanometer-size quantum thin line is formed on a semiconductor substrate of a Si substrate or the like by means of the general film forming technique, lithographic technique and etching technique. By opportunely using the conventional film forming technique, photolithographic technique and etching technique, a second oxide film that extends in the perpendicular direction is formed on an Si substrate. Then, by removing the second oxide film that extends in the perpendicular direction, a second nitride film located below the film and a first oxide film located below the film by etching, a groove for exposing the Si substrate is formed. Then, a Si thin line is made to epitaxially grow on the exposed portion of the Si substrate. The quantum thin line is thus formed without using any special fine processing technique. The width of the groove can be accurately controlled in nanometers by controlling the film thickness of the second oxide film that is formed by oxidizing the surface of the second nitride film.

Abstract: An amorphous silicon film is deposited on a quartz substrate, and a metal of Ni is introduced into the amorphous silicon film so that the amorphous silicon film is crystallized. Phosphorus is ion-implanted with an oxide pattern used as a mask. A heating process is performed in a nitrogen atmosphere, by which Ni is gettered. A heating process is performed in an O2 atmosphere, by which Ni is gettered into the oxide. Like this, by performing the first gettering in a non-oxidative atmosphere, the Ni concentration can be reduced to such a level that oxidation does not cause any increase of irregularities or occurrence of pinholes. Thus, in a second gettering, enough oxidation can be effected without minding any increase of irregularities and occurrence of pinholes, so that the Ni concentration can be reduced to an extremely low level. Also, a high-quality crystalline silicon film free from surface irregularities and pinholes can be obtained.

Abstract: There is provided a microstructure producing method capable of achieving satisfactory uniformity and reproducibility of the growth position, size and density of a minute particle or thin line and materializing a semiconductor device which can reduce the cost through simple processes without using any special microfabrication technique and has superior characteristics appropriate for mass-production with high yield and high productivity as well as a semiconductor device employing the microstructure. An oxide film 12 having a region 12a of a great film thickness and a region 12b of a small film thickness are formed on the surface of a semiconductor substrate 11. Next, a microstructure that is a thin line 15 made of silicon Si is selectively formed only on the surface of the small-film-thickness region 12b of the oxide film 12.

Abstract: There is provided a semiconductor manufacturing method capable of sufficiently reducing catalytic element in a crystalline silicon film and also increasing the area of the crystalline silicon film to be left on the substrate. A catalytic element for accelerating the crystallization is introduced into an amorphous silicon film on a substrate, and a first heat treatment is performed to crystallize the amorphous silicon film into a crystalline silicon film. A mask layer is provided on the surface of the crystalline silicon film, the mask layer having an opening passing thicknesswise through the mask layer. Further thereon, a sacrifice film is formed so as to continuously cover the surface of the mask layer and an opening-correspondent portion of the crystalline silicon film. A getter element for gettering the catalytic element is introduced into the sacrifice film and the opening-correspondent portion of the crystalline silicon film.

Abstract: There is provided is a semiconductor storage device that can reduce a dispersion in characteristics such as a threshold voltage and a writing performance and has a low consumption power and a non-volatility. There are included a source region 9 and a drain region 10 formed on a silicon substrate 1, a channel region 3a located between the source and drain regions 9 and 10, a gate electrode 8 that is formed above the channel region 3a and controls a channel current flowing through the channel region 3a, and a control gate insulating film 7, a floating gate 6 and a tunnel insulating film 4 that are arranged in order from the gate electrode 8 side between the channel region 3a and the gate electrode 8. The floating gate 6 is comprised of a plurality of crystal grains 6a linearly discretely arranged substantially parallel to the surface of the channel region 3a.

Abstract: A Si protruding portion is formed on a Si substrate by opportunely using the general film forming technique, photolithographic technique and etching technique. A second oxide film is formed to fill up a space between Si protruding portions, and the surface is flattened by the CMP method or the like. Then, the second oxide film is subjected to anisotropic etching to form a Si exposed portion at the top of the Si protruding portion. A Si thin line is made to grow in this Si exposed portion, and then a third oxide film for isolating the Si thin line from the Si substrate is formed through oxidation. A quantum thin line is thus formed at low cost without using any special technique of SOI or the like. Furthermore, the substrate surface is flattened, allowing the formation of a single electron device or a quantum effect device to be easy. The quantum thin line is isolated from the Si substrate by the third oxide film, completely confining the electron.