Patents by Inventor Yasunari Umemoto

Yasunari Umemoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200402932
    Abstract: A semiconductor element includes a semiconductor substrate, first and second amplifiers provided on the semiconductor substrate and adjacently provided in a first direction, a first reference potential bump provided on a main surface of the semiconductor substrate, and connecting the first amplifier and a reference potential, a second reference potential bump provided on the main surface, being adjacent to the first reference potential bump in the first direction, and connecting the second amplifier and a reference potential, and a rectangular bump provided on the main surface, provided between the first and second reference potential bumps in a plan view, and formed such that a second width in a second direction orthogonal to the first direction is larger than a first width in the first direction. The second width is larger than a width of at least one of the first and second reference potential bumps in the second direction.
    Type: Application
    Filed: June 18, 2020
    Publication date: December 24, 2020
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Shigeki KOYA, Yasunari UMEMOTO, Isao OBU, Masao KONDO, Yuichi SAITO, Takayuki TSUTSUI
  • Publication number: 20200382083
    Abstract: A power amplifier includes initial-stage and output-stage amplifier circuits, and initial-stage and output-stage bias circuits. The initial-stage amplifier circuit includes a first high electron mobility transistor having a source electrically connected to a reference potential, and a gate to which a radio-frequency input signal is inputted, and a first heterojunction bipolar transistor having an emitter electrically connected to a drain of the first high electron mobility transistor, a base electrically connected to the reference potential in an alternate-current fashion, and a collector to which direct-current power is supplied and from which a radio-frequency signal is outputted.
    Type: Application
    Filed: August 18, 2020
    Publication date: December 3, 2020
    Inventors: Isao OBU, Satoshi TANAKA, Takayuki TSUTSUI, Yasunari UMEMOTO
  • Patent number: 10855232
    Abstract: A power amplifier module includes a first amplifier circuit that amplifies a radio frequency signal with a first gain corresponding to a first control signal to generate a first amplified signal; a second amplifier circuit that amplifies the first amplified signal with a second gain corresponding to a second control signal to generate a second amplified signal; and a control unit that generates the first control signal and the second control signal. The second control signal is a control signal for increasing a power-supply voltage for the second amplifier circuit as a peak-to-average power ratio of the radio frequency signal increases. The first control signal is a control signal for controlling the first gain of the first amplifier circuit so that a variation in the second gain involved in a variation in the power-supply voltage for the second amplifier circuit is compensated for.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: December 1, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Shigeki Koya, Takayuki Tsutsui, Yasunari Umemoto, Isao Obu, Satoshi Tanaka
  • Publication number: 20200373417
    Abstract: A heterojunction bipolar transistor includes a collector layer, a base layer, and an emitter layer that are stacked on a substrate. The collector layer includes a graded semiconductor layer in which an electron affinity increases from a side closer to the base layer toward a side farther from the base layer. An electron affinity of the base layer at an interface closer to the collector layer is equal to an electron affinity of the graded semiconductor layer at an interface closer to the base layer.
    Type: Application
    Filed: August 12, 2020
    Publication date: November 26, 2020
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari UMEMOTO, Shigeki KOYA, Isao OBU
  • Publication number: 20200357699
    Abstract: A collector layer, a base layer, an emitter layer, and an emitter mesa layer are placed above a substrate in this order. A base electrode and an emitter electrode are further placed above the substrate. The emitter mesa layer has a long shape in a first direction in plan view. The base electrode includes a base electrode pad portion spaced from the emitter mesa layer in the first direction. An emitter wiring line and a base wiring line are placed on the emitter electrode and the base electrode, respectively. The emitter wiring line is connected to the emitter electrode via an emitter contact hole. In the first direction, the spacing between the edges of the emitter mesa layer and the emitter contact hole on the side of the base wiring line is smaller than that between the emitter mesa layer and the base wiring line.
    Type: Application
    Filed: May 7, 2020
    Publication date: November 12, 2020
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari UMEMOTO, Shigeki KOYA, Isao OBU, Kaoru IDENO
  • Publication number: 20200335611
    Abstract: A bipolar transistor has a subcollector layer and a stack of collector, base, and emitter layers on the subcollector layer. On the subcollector layer are collector electrodes. On the base layer are base electrodes. The collector layer includes multiple doped layers with graded impurity concentrations, higher on the subcollector layer side and lower on the base layer side. Of these doped layers, the one having the highest impurity concentration is in contact with the subcollector layer and has a sheet resistance less than or equal to about nine times that of the subcollector layer.
    Type: Application
    Filed: July 2, 2020
    Publication date: October 22, 2020
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari UMEMOTO, Shigeki KOYA, Atsushi KUROKAWA
  • Publication number: 20200303372
    Abstract: A semiconductor device includes two cell rows, each of which is formed of a plurality of transistor cells aligned in parallel to each other. Each of the plurality of transistor cells includes a collector region, a base region, and an emitter region that are disposed above a substrate. A plurality of collector extended wiring lines are each connected to the collector region of a corresponding one of the plurality of transistor cells and are extended in a direction intersecting an alignment direction of the plurality of transistor cells. A collector integrated wiring line connects the plurality of collector extended wiring lines to each other. A collector intermediate integrated wiring line that is disposed between the two cell rows in plan view connects the plurality of collector extended wring lines extended from the plurality of transistor cells that belong to one of the two cell rows to each other.
    Type: Application
    Filed: March 16, 2020
    Publication date: September 24, 2020
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Kenji SASAKI, Masao KONDO, Shigeki KOYA, Shinnosuke TAKAHASHI, Yasunari UMEMOTO, Isao OBU, Takayuki TSUTSUI
  • Patent number: 10777669
    Abstract: A heterojunction bipolar transistor includes a collector layer, a base layer, and an emitter layer that are stacked on a substrate. The collector layer includes a graded semiconductor layer in which an electron affinity increases from a side closer to the base layer toward a side farther from the base layer. An electron affinity of the base layer at an interface closer to the collector layer is equal to an electron affinity of the graded semiconductor layer at an interface closer to the base layer.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: September 15, 2020
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari Umemoto, Shigeki Koya, Isao Obu
  • Patent number: 10778159
    Abstract: A power amplifier includes initial-stage and output-stage amplifier circuits, and initial-stage and output-stage bias circuits. The initial-stage amplifier circuit includes a first high electron mobility transistor having a source electrically connected to a reference potential, and a gate to which a radio-frequency input signal is inputted, and a first heterojunction bipolar transistor having an emitter electrically connected to a drain of the first high electron mobility transistor, a base electrically connected to the reference potential in an alternate-current fashion, and a collector to which direct-current power is supplied and from which a radio-frequency signal is outputted.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: September 15, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Isao Obu, Satoshi Tanaka, Takayuki Tsutsui, Yasunari Umemoto
  • Publication number: 20200287027
    Abstract: A semiconductor device includes a collector layer, a base layer, and an emitter layer that are disposed above a substrate. An emitter mesa layer is disposed on a partial region of the emitter layer. In a plan view, the base electrode is disposed in or on a region which does not overlap the emitter mesa layer. The base electrode allows base current to flow to the base layer. In the plan view, a first edge forming part of edges of the emitter mesa layer extends in a first direction, and a second edge forming part of edges of the base electrode faces the first edge. A gap between the first edge and the second edge in a terminal portion located in an end portion of the emitter mesa layer in the first direction is wider than a gap in an intermediate portion of the emitter mesa layer.
    Type: Application
    Filed: March 5, 2020
    Publication date: September 10, 2020
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari UMEMOTO, Isao OBU, Kaoru IDENO, Shigeki KOYA
  • Patent number: 10741680
    Abstract: A bipolar transistor has a subcollector layer and a stack of collector, base, and emitter layers on the subcollector layer. On the subcollector layer are collector electrodes. On the base layer are base electrodes. The collector layer includes multiple doped layers with graded impurity concentrations, higher on the subcollector layer side and lower on the base layer side. Of these doped layers, the one having the highest impurity concentration is in contact with the subcollector layer and has a sheet resistance less than or equal to about nine times that of the subcollector layer.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: August 11, 2020
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari Umemoto, Shigeki Koya, Atsushi Kurokawa
  • Publication number: 20200251579
    Abstract: A bipolar transistor includes a collector layer, a base layer, and an emitter layer that are formed in this order on a compound semiconductor substrate. The emitter layer is disposed inside an edge of the base layer in plan view. A base electrode is disposed on partial regions of the emitter layer and the base layer so as to extend from an inside of the emitter layer to an outside of the base layer in plan view. An insulating film is disposed between the base electrode and a portion of the base layer, with the portion not overlapping the emitter layer. An alloy layer extends from the base electrode through the emitter layer in a thickness direction and reaches the base layer. The alloy layer contains at least one element constituting the base electrode and elements constituting the emitter layer and the base layer.
    Type: Application
    Filed: April 21, 2020
    Publication date: August 6, 2020
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Isao OBU, Yasunari UMEMOTO, Masahiro SHIBATA, Shigeki KOYA, Masao KONDO, Takayuki TSUTSUI
  • Publication number: 20200219995
    Abstract: A collector layer of an HBT includes a high-concentration collector layer and a low-concentration collector layer thereon. The low-concentration collector layer includes a graded collector layer in which the energy band gap varies to narrow with increasing distance from the base layer. The electron affinity of the semiconductor material for the base layer is greater than that of the semiconductor material for the graded collector layer at the point of the largest energy band gap by about 0.15 eV or less. The electron velocity in the graded collector layer peaks at a certain electric field strength. In the graded collector layer, the strength of the quasi-electric field, an electric field that acts on electrons as a result of the varying energy band gap, is between about 0.3 times and about 1.8 times the peak electric field strength, the electric field strength at which the electron velocity peaks.
    Type: Application
    Filed: March 18, 2020
    Publication date: July 9, 2020
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari UMEMOTO, Shigeki KOYA, Isao OBU
  • Publication number: 20200177140
    Abstract: A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.
    Type: Application
    Filed: February 7, 2020
    Publication date: June 4, 2020
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Isao OBU, Yasunari UMEMOTO, Masahiro SHIBATA, Kenichi NAGURA
  • Patent number: 10665519
    Abstract: A semiconductor chip includes a single-crystal substrate and a metal electrode on the bottom surface of the substrate. The metal electrode has a region in which a first metal is exposed and a region in which a second metal is exposed, the second metal having a standard electrode potential different from that of the first metal.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: May 26, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Isao Obu, Yasunari Umemoto, Masahiro Shibata
  • Patent number: 10665704
    Abstract: A bipolar transistor includes a collector layer, a base layer, and an emitter layer that are formed in this order on a compound semiconductor substrate. The emitter layer is disposed inside an edge of the base layer in plan view. A base electrode is disposed on partial regions of the emitter layer and the base layer so as to extend from an inside of the emitter layer to an outside of the base layer in plan view. An insulating film is disposed between the base electrode and a portion of the base layer, with the portion not overlapping the emitter layer. An alloy layer extends from the base electrode through the emitter layer in a thickness direction and reaches the base layer. The alloy layer contains at least one element constituting the base electrode and elements constituting the emitter layer and the base layer.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: May 26, 2020
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Isao Obu, Yasunari Umemoto, Masahiro Shibata, Shigeki Koya, Masao Kondo, Takayuki Tsutsui
  • Patent number: 10636897
    Abstract: In a bipolar transistor, a collector layer includes three semiconductor layers: an n-type GaAs layer (Si concentration: about 5×1015 cm?3, thickness: about 350 nm), a p-type GaAs layer (C concentration: about 4.5×1015 cm?3, thickness: about 100 nm, sheet concentration: 4.5×1010 cm?2), and an n-type GaAs layer Si concentration: about 5×1015 cm?3, thickness: about 500 nm. The sheet concentration of the p-type GaAs layer is set to less than 1×1011 cm?2.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: April 28, 2020
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari Umemoto, Atsushi Kurokawa, Tsunekazu Saimei
  • Patent number: 10629712
    Abstract: A collector layer of an HBT includes a high-concentration collector layer and a low-concentration collector layer thereon. The low-concentration collector layer includes a graded collector layer in which the energy band gap varies to narrow with increasing distance from the base layer. The electron affinity of the semiconductor material for the base layer is greater than that of the semiconductor material for the graded collector layer at the point of the largest energy band gap by about 0.15 eV or less. The electron velocity in the graded collector layer peaks at a certain electric field strength. In the graded collector layer, the strength of the quasi-electric field, an electric field that acts on electrons as a result of the varying energy band gap, is between about 0.3 times and about 1.8 times the peak electric field strength, the electric field strength at which the electron velocity peaks.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: April 21, 2020
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari Umemoto, Shigeki Koya, Isao Obu
  • Publication number: 20200119171
    Abstract: A bipolar transistor has a subcollector layer and a stack of collector, base, and emitter layers on the subcollector layer. On the subcollector layer are collector electrodes. On the base layer are base electrodes. The collector layer includes multiple doped layers with graded impurity concentrations, higher on the subcollector layer side and lower on the base layer side. Of these doped layers, the one having the highest impurity concentration is in contact with the subcollector layer and has a sheet resistance less than or equal to about nine times that of the subcollector layer.
    Type: Application
    Filed: December 11, 2019
    Publication date: April 16, 2020
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari UMEMOTO, Shigeki KOYA, Atsushi KUROKAWA
  • Patent number: 10594271
    Abstract: A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: March 17, 2020
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Isao Obu, Yasunari Umemoto, Masahiro Shibata, Kenichi Nagura