Patents by Inventor Yasunobu Akizuki

Yasunobu Akizuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11550589
    Abstract: A calculation processing apparatus includes a decoder that decodes memory access instructions including a store instruction and a load instruction; a first queue that stores the decoded memory access instructions; a second queue that stores store data related to the store instruction; a storage circuit that stores target address information of the store instruction for which the first queue is reserved but the second queue is not reserved; and an inhibitor that inhibits execution of the load instruction when address information matching target address information of the load instruction is stored in the storage circuit when the load instruction is being processed. This configuration inhibits switching of the order of a store instruction and a load instruction.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: January 10, 2023
    Assignee: FUJITSU LIMITED
    Inventors: Takekazu Tabata, Yasunobu Akizuki, Sota Sakashita
  • Patent number: 11442861
    Abstract: A semiconductor device includes a plurality of cores, each including an instruction execution circuit and a first cache, and a second cache shared by the plurality of cores. In each of the cores, a number of completed instructions for each type of the instructions executed by the instruction execution circuit are counted, and an execution frequency for each type of instructions are calculated. Based on the execution frequencies, a cache line size preferable for use in the first cache in the core is selected. Based on the selected preferable cache line sizes for the cores, a cache line size used in the first caches and the second cache is determined.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: September 13, 2022
    Assignee: FUJITSU LIMITED
    Inventor: Yasunobu Akizuki
  • Patent number: 11372712
    Abstract: A processing device performs a first process in a plurality of cycles to update a plurality of resources included in programmable resources. The processing device includes an instruction execution circuit that records that the first process is being executed, and makes an error notification when an error is detected during execution of an instruction, and a retry control circuit that records a type of the first process at a starting point of the first process, judges from the recorded type whether the first process is re-executable upon receiving the error notification during the first process, and instructs re-execution of the first process from a start of the first process in a case where the first process is judged to be re-executable. The instruction execution circuit performs a retry process to re-execute the first process when instructed from the retry control circuit to re-execute the first process.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: June 28, 2022
    Assignee: FUJITSU LIMITED
    Inventors: Norihito Gomyo, Ryohei Okazaki, Yasunobu Akizuki
  • Patent number: 11249763
    Abstract: An arithmetic processing unit includes an instruction decoder which decodes a fetch instruction to issue an execution instruction; a reservation station which temporarily stores the execution instruction; and an arithmetic unit which executes the execution instruction, and the fetch instruction includes a multi-flow instruction which is divided into divided instructions and a single instruction. The instruction decoder includes: a pre-decoder including N number of slots each of which divides the multi-flow instruction into divided instructions; a main decoder including N number of slots each of which decodes the instructions to issue an execution instruction; and a pre-decoder buffer including N?K number of slots each of which temporarily stores instructions in the pre-decoder. The instruction decoder repeats transferring the divided instructions and the single instructions from the slots of the pre-decoder and the slots of the pre-decoder buffer to the main decoder as much as possible in order.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: February 15, 2022
    Assignee: FUJITSU LIMITED
    Inventors: Ryohei Okazaki, Yasunobu Akizuki
  • Publication number: 20220027274
    Abstract: A semiconductor device includes a plurality of cores, each including an instruction execution circuit and a first cache, and a second cache shared by the plurality of cores. In each of the cores, a number of completed instructions for each type of the instructions executed by the instruction execution circuit are counted, and an execution frequency for each type of instructions are calculated. Based on the execution frequencies, a cache line size preferable for use in the first cache in the core is selected. Based on the selected preferable cache line sizes for the cores, a cache line size used in the first caches and the second cache is determined.
    Type: Application
    Filed: June 2, 2021
    Publication date: January 27, 2022
    Applicant: FUJITSU LIMITED
    Inventor: YASUNOBU AKIZUKI
  • Patent number: 10996954
    Abstract: By including a storing device that stores a plurality of memory access instructions decoded by a decoder and outputs the memory access instruction stored therein to a cache memory, a determiner that determines whether the storing device is afford to store the plurality of memory access instructions; and an inhibitor that inhibits, when the determiner determines that the storing device is not afford to store a first memory access instruction included in the plurality of memory access instructions, execution of a second memory access instruction being included in the plurality of memory access instructions and being subsequent to the first memory access instruction for a predetermined time period, regardless of a result of determination made on the second memory access instruction by the determiner, the calculation processing apparatus inhibits a switch of the order of a store instruction and a load instruction.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: May 4, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Sota Sakashita, Yasunobu Akizuki
  • Patent number: 10831482
    Abstract: An arithmetic processing apparatus includes a decoder, a first cache memory, a second cache memory and a processor. The processor performs a cache hit determination on the first cache memory in response to a memory access instruction, issues a data request to a second cache memory when the cache hit determination is a cache miss. When the memory access instruction is for a speculative execution speculatively executed in a state where a branch destination of a branch instruction is unestablished, the decoder issues the memory access instruction with a valid prohibition flag and an instruction identifier. In a case where the cache hit determination is the cache miss and the prohibition flag is valid, the processor does not issue the data request to the second cache memory. In a case where the cache hit determination is a cache hit, the processor acquires data from the first cache memory.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: November 10, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Yasunobu Akizuki, Toshio Yoshida
  • Patent number: 10824431
    Abstract: An arithmetic circuit performs a floating-point operation. A floating-point register includes entries each allocated to an architectural register or a renaming register. An operation execution controller circuit issues a floating-point operation instruction and outputs a termination report of the floating-point operation before the floating-point operation is terminated. When exception handling is not performed at the time of instruction completion even when an exception is detected in the operation of the floating-point operation instruction, an instruction completion controller circuit outputs a release instruction that indicates a release of a renaming register when instruction execution is completed after the termination report is received.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: November 3, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Yasunobu Akizuki, Atushi Fusejima, Norihito Gomyo, Ryohei Okazaki
  • Publication number: 20200183694
    Abstract: A calculation processing apparatus includes a decoder that decodes memory access instructions including a store instruction and a load instruction; a first queue that stores the decoded memory access instructions; a second queue that stores store data related to the store instruction; a storage circuit that stores target address information of the store instruction for which the first queue is reserved but the second queue is not reserved; and an inhibitor that inhibits execution of the load instruction when address information matching target address information of the load instruction is stored in the storage circuit when the load instruction is being processed. This configuration inhibit switching of the order of a store instruction and a load instruction.
    Type: Application
    Filed: November 27, 2019
    Publication date: June 11, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Takekazu Tabata, Yasunobu Akizuki, Sota Sakashita
  • Publication number: 20200167226
    Abstract: A processing device performs a first process in a plurality of cycles to update a plurality of resources included in programmable resources. The processing device includes an instruction execution circuit that records that the first process is being executed, and makes an error notification when an error is detected during execution of an instruction, and a retry control circuit that records a type of the first process at a starting point of the first process, judges from the recorded type whether the first process is re-executable upon receiving the error notification during the first process, and instructs re-execution of the first process from a start of the first process in a case where the first process is judged to be re-executable. The instruction execution circuit performs a retry process to re-execute the first process when instructed from the retry control circuit to re-execute the first process.
    Type: Application
    Filed: November 12, 2019
    Publication date: May 28, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Norihito Gomyo, Ryohei Okazaki, YASUNOBU AKIZUKI
  • Publication number: 20200117459
    Abstract: By including a storing device that stores a plurality of memory access instructions decoded by a decoder and outputs the memory access instruction stored therein to a cache memory, a determiner that determines whether the storing device is afford to store the plurality of memory access instructions; and an inhibitor that inhibits, when the determiner determines that the storing device is not afford to store a first memory access instruction included in the plurality of memory access instructions, execution of a second memory access instruction being included in the plurality of memory access instructions and being subsequent to the first memory access instruction for a predetermined time period, regardless of a result of determination made on the second memory access instruction by the determiner, the calculation processing apparatus inhibits a switch of the order of a store instruction and a load instruction.
    Type: Application
    Filed: October 7, 2019
    Publication date: April 16, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Sota Sakashita, YASUNOBU AKIZUKI
  • Publication number: 20190384608
    Abstract: An arithmetic circuit performs a floating-point operation. A floating-point register includes entries each allocated to an architectural register or a renaming register. An operation execution controller circuit issues a floating-point operation instruction and outputs a termination report of the floating-point operation before the floating-point operation is terminated. When exception handling is not performed at the time of instruction completion even when an exception is detected in the operation of the floating-point operation instruction, an instruction completion controller circuit outputs a release instruction that indicates a release of a renaming register when instruction execution is completed after the termination report is received.
    Type: Application
    Filed: May 20, 2019
    Publication date: December 19, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Yasunobu Akizuki, Atushi Fusejima, Norihito Gomyo, Ryohei Okazaki
  • Publication number: 20190377576
    Abstract: An arithmetic processing apparatus includes a decoder, a first cache memory, a second cache memory and a processor. The processor performs a cache hit determination on the first cache memory in response to a memory access instruction, issues a data request to a second cache memory when the cache hit determination is a cache miss. When the memory access instruction is for a speculative execution speculatively executed in a state where a branch destination of a branch instruction is unestablished, the decoder issues the memory access instruction with a valid prohibition flag and an instruction identifier. In a case where the cache hit determination is the cache miss and the prohibition flag is valid, the processor does not issue the data request to the second cache memory. In a case where the cache hit determination is a cache hit, the processor acquires data from the first cache memory.
    Type: Application
    Filed: May 30, 2019
    Publication date: December 12, 2019
    Applicant: FUJITSU LIMITED
    Inventors: YASUNOBU AKIZUKI, Toshio Yoshida
  • Patent number: 10496540
    Abstract: A processor includes a cache memory, an issuing unit that issues, with respect to all element data as a processing object of a load instruction, a cache request to the cache memory for each of a plurality of groups which are divided to include element data, a comparing unit that compares addresses of the element data as the processing object of the load instruction, and determines whether element data in a same group are simultaneously accessible, and a control unit that accesses the cache memory according to the cache request registered in a load queue registering one or more cache requests issued from the issuing unit. The control unit processes by one access whole element data determined to be simultaneously accessible by the comparing unit.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: December 3, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Hideki Okawara, Noriko Takagi, Yasunobu Akizuki, Kenichi Kitamura, Mikio Hondo
  • Patent number: 10430196
    Abstract: An arithmetic processing device includes: a branch prediction unit configured to predict a branch destination address and loop processing based on an address generated by an address generation unit; an instruction buffer unit configured to store an instruction of the address generated by the address generation unit; an instruction decoding unit configured to decode the instruction stored in the instruction buffer unit; and a loop buffer unit configured to store decoding results or decoding intermediate results of instructions of the predicted loop processing that are decoded by the instruction decoding unit and output the stored decoding results or decoding intermediate results a predetermined number of times in response to the loop processing, in which during a period when selecting the output of the loop buffer unit, operations of the address generation unit, the branch prediction unit, the instruction buffer unit, and the instruction decoding unit are stopped.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: October 1, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Ryohei Okazaki, Norihito Gomyo, Yasunobu Akizuki, Takashi Suzuki
  • Publication number: 20190294435
    Abstract: An arithmetic processing unit includes an instruction decoder which decodes a fetch instruction to issue an execution instruction; a reservation station which temporarily stores the execution instruction; and an arithmetic unit which executes the execution instruction, and the fetch instruction includes a multi-flow instruction which is divided into divided instructions and a single instruction. The instruction decoder includes: a pre-decoder including N number of slots each of which divides the multi-flow instruction into divided instructions; a main decoder including N number of slots each of which decodes the instructions to issue an execution instruction; and a pre-decoder buffer including N?K number of slots each of which temporarily stores instructions in the pre-decoder. The instruction decoder repeats transferring the divided instructions and the single instructions from the slots of the pre-decoder and the slots of the pre-decoder buffer to the main decoder as much as possible in order.
    Type: Application
    Filed: February 4, 2019
    Publication date: September 26, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Ryohei Okazaki, YASUNOBU AKIZUKI
  • Patent number: 9965283
    Abstract: A first entry, when outputting an instruction stored in the first entry to a first arithmetic unit and when an execution cycle number of the instruction stored in the first entry is equal to or more than a threshold value, outputs a use inability signal of the first arithmetic unit to a second entry, a reservation station includes a controller configured to, when the use inability signal of the first arithmetic unit is output and then a use inability discontinuation condition is satisfied, perform control to discontinue execution of the first arithmetic unit, store a state of the first arithmetic unit in a storage element, and discontinue output of the use inability signal of the first arithmetic unit, and the second entry, when output of the use inability signal of the first arithmetic unit is discontinued, outputs an instruction stored in the second entry to the first arithmetic unit.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: May 8, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Ryohei Okazaki, Yasunobu Akizuki, Takekazu Tabata
  • Patent number: 9952872
    Abstract: An arithmetic processing device includes an instruction decode unit, an instruction execution unit and an instruction hold unit, wherein the instruction hold unit includes; a first holder including a plurality of first entries each configured to hold a decoded instruction; a second holder including a smaller number of second entries than the number of the first entries; a first selector configured to select an instruction to be registered in the second holder from instructions held in the first entries and store identification information that identifies the selected instruction into any of the second entries; and a second selector configured to sequentially select an executable instruction from instructions registered in the second holder, input the selected executable instruction to the instruction execution unit, and detect a dependency between the instruction inputted to the instruction execution unit and the instructions registered in the second holder.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: April 24, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Sota Sakashita, Yasunobu Akizuki
  • Publication number: 20180004528
    Abstract: An arithmetic processing device includes: a branch prediction unit configured to predict a branch destination address and loop processing based on an address generated by an address generation unit; an instruction buffer unit configured to store an instruction of the address generated by the address generation unit; an instruction decoding unit configured to decode the instruction stored in the instruction buffer unit; and a loop buffer unit configured to store decoding results or decoding intermediate results of instructions of the predicted loop processing that are decoded by the instruction decoding unit and output the stored decoding results or decoding intermediate results a predetermined number of times in response to the loop processing, in which during a period when selecting the output of the loop buffer unit, operations of the address generation unit, the branch prediction unit, the instruction buffer unit, and the instruction decoding unit are stopped.
    Type: Application
    Filed: May 22, 2017
    Publication date: January 4, 2018
    Applicant: FUJITSU LIMITED
    Inventors: Ryohei Okazaki, Norihito Gomyo, YASUNOBU AKIZUKI, Takashi Suzuki
  • Publication number: 20170060748
    Abstract: A processor includes a cache memory, an issuing unit that issues, with respect to all element data as a processing object of a load instruction, a cache request to the cache memory for each of a plurality of groups which are divided to include element data, a comparing unit that compares addresses of the element data as the processing object of the load instruction, and determines whether element data in a same group are simultaneously accessible, and a control unit that accesses the cache memory according to the cache request registered in a load queue registering one or more cache requests issued from the issuing unit. The control unit processes by one access whole element data determined to be simultaneously accessible by the comparing unit.
    Type: Application
    Filed: July 27, 2016
    Publication date: March 2, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Hideki Okawara, Noriko Takagi, YASUNOBU AKIZUKI, Kenichi Kitamura, Mikio Hondo