Patents by Inventor Yasunori Abe

Yasunori Abe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070076329
    Abstract: A magnetic encoder having a magnetic sensor composed of SVGMR elements, in which a signal output with a half of a cycle of magnetic regions on a magnetic medium. The magnetic encoder comprises the magnetic medium, on which first magnetic regions and second magnetic regions are oppositely magnetized along the medium extending and disposed successively and alternately with each other, and the magnetic sensor that has an even number of SVGMR elements and is movable relatively to the medium along the medium extending. Magnetizations of pinned magnetization layers of all the SVGMR elements are directed in a same direction along the medium extending.
    Type: Application
    Filed: September 18, 2006
    Publication date: April 5, 2007
    Inventors: Yasunori Abe, Yuji Nihei
  • Publication number: 20070030587
    Abstract: A fall detection device is provided, which accomplishes a fall judgment on acceleration by a simple calculation and improves uniformity of effective threshold value for the acceleration judgment as to a direction of an applied acceleration vector. The fall detection device produces a fall detection signal, when an absolute value of each axis component of an acceleration measured by a three-axis acceleration sensor is less than a first threshold value, and when a sum of the absolute values of the axis components of the acceleration is less than a second threshold value that is 1.5 times to twice the first threshold value.
    Type: Application
    Filed: July 14, 2006
    Publication date: February 8, 2007
    Inventors: Masaru Noda, Yasunori Abe
  • Patent number: 7138798
    Abstract: An azimuth meter using spin-valve giant magneto-resistive elements, which is simple in manufacturing process, can be made compact in size and contribute to power saving, is disclosed. The azimuth meter comprises a quadrilateral plane coil having two pairs of parallel opposed sides and four spin-valve giant magneto-resistive element pairs, each pair of the elements disposed on a plane parallel to the coil. The longitudinal directions of two elements of each pair orthogonally cross each other, and cross only a respective side or only the same side of a pair of the opposed sides of the plane coil at substantially 45 degrees. The pinned layer of one of the two elements is magnetized in its longitudinal direction, and that of the other element is magnetized in the same direction as the pinned layer of that one element. The paired elements are connected to each other at one end.
    Type: Grant
    Filed: July 6, 2005
    Date of Patent: November 21, 2006
    Assignee: Hitachi Metals, Ltd.
    Inventors: Yasunori Abe, Kazuo Suzuki
  • Publication number: 20060236761
    Abstract: A free fall detection device capable of detecting a fall accompanied by rotation is provided. A fall accompanied by rotation is detected based on a waveform of an acceleration signal output from the acceleration detection unit and an angular velocity signal output from the angular velocity detection unit. A gravity center acceleration of the device to be protected is calculated from the acceleration detected by the acceleration detection unit and from the angular velocity detected by the angular velocity detection unit. Even when the device being protected rotates as it falls, the fall of the device can be detected from the detected acceleration or angular velocity. Further, by calculating the gravity center acceleration not affected by the rotation, it is possible to detect a fall of the device with high precision even if the device rotates as it falls.
    Type: Application
    Filed: February 17, 2006
    Publication date: October 26, 2006
    Applicant: Hitachi Metals, Ltd.
    Inventors: Hideki Inoue, Munetoshi Unuma, Yasunori Abe, Masakatsu Saitoh
  • Publication number: 20060111885
    Abstract: In delay characteristic evaluation of a logical circuit, there was the problem of underestimation of the output load compared with the actual output load. There is provided a simulation device including a simplification section that, simplifies the load circuit using a transistor with which a virtual control voltage source is connected, by specifying a transistor driven through the output terminal of the target circuit and connecting to the drain of this transistor the virtual control voltage source whereby the output potential of this transistor is varied in accordance with the gate potential of this transistor.
    Type: Application
    Filed: February 28, 2005
    Publication date: May 25, 2006
    Applicant: FUJITSU LIMITED
    Inventor: Yasunori Abe
  • Patent number: 6826842
    Abstract: To provide a thin and small area azimuth meter. A plane coil and at least two groups of thin film magneto resistive elements are arranged. Each of the groups of thin film magneto resistive elements constitutes an MR bridge and detects and outputs two perpendicular components of the earth magnetism, and bearing information is obtained based on the output values.
    Type: Grant
    Filed: October 6, 2003
    Date of Patent: December 7, 2004
    Assignee: Hitachi Metals, Ltd.
    Inventors: Yasunori Abe, Osamu Shimoe
  • Publication number: 20040111906
    Abstract: To provide a thin and small-area azimuth meter. A plane coil and at least two groups of thin film magneto resistive elements are arranged. Each of the groups of thin film magneto resistive elements constitutes an MR bridge and detects and outputs two perpendicular components of the earth magnetism, and bearing information is obtained based on the output values.
    Type: Application
    Filed: October 6, 2003
    Publication date: June 17, 2004
    Inventors: Yasunori Abe, Osamu Shimoe
  • Patent number: 6560763
    Abstract: A route searching method is used for circuit design, and includes a step of setting, with respect to each pin, a corresponding flag of a pass flag which indicates that a pin is passed, a searching flag which indicates that a pin is being searched, and a branch flag which indicates that a pin is a branch point, and a step of determining a direction of a route search depending on each flag which is set with respect to each pin.
    Type: Grant
    Filed: August 14, 2000
    Date of Patent: May 6, 2003
    Assignee: Fujitsu Limited
    Inventors: Hiroyuki Sugiyama, Yasunori Abe, Naomi Bizen, Hiroshi Ikeda
  • Patent number: 6556007
    Abstract: To provide a bearing sensor having a thin plane coil for applying a biasing magnetic field and at least one magneto resistive element pair (a first magneto resistive thin plate and a second magneto resistive thin plate) crossing opposed conductor sides of the coil. The plane coil has at least one pair of opposed conductor sides (a first side and a second side). The first magneto resistive thin plate and the first side cross one another at an angle more than 30 degrees and less than 90 degrees. The second magneto resistive thin plate and the second side cross one another at an angle more than 30 degrees and less than 90 degrees. While biasing magnetic fields in opposite directions are applied to the magneto resistive thin plates, respectively, intermediate potentials of the magneto resistive element pair are measured to determine bearings based on the difference between the intermediate potentials.
    Type: Grant
    Filed: January 29, 2002
    Date of Patent: April 29, 2003
    Assignee: Hitachi Metals, Ltd.
    Inventors: Yasunori Abe, Osamu Shimoe, Yukimasa Shonowaki, Hiromitsu Itabashi, Hiroyuki Mima, Hitoshi Harata
  • Patent number: 6308305
    Abstract: There are disclosed a method and an apparatus for circuit designing, which enable arranging and wiring operations to be efficiently performed by using indices for arranging and wiring without the occurrence of any error paths. In the method and apparatus for circuit designing, path tracing is performed from one or more tracing start pins for a result of logical designing and the number of passing through each pin of cells to be arranged is counted during the path tracing. Thus, the method and apparatus for circuit designing are suitably used for designing of a circuit such as a LSI or the like, which has been enlarged in size and complex following an advance in a micro fabrication art.
    Type: Grant
    Filed: June 13, 1997
    Date of Patent: October 23, 2001
    Assignee: Fujitsu Limited
    Inventors: Hiroyuki Sugiyama, Yasunori Abe, Naomi Bizen
  • Patent number: 6240541
    Abstract: A circuit designing apparatus of an interactive type which enables a simplified and highspeed circuit design process while largely reducing a burden on a designer, having a speed analyzing unit for conducting a delay computation for each wiring path on a circuit to be designed and a display control unit for displaying a result of the delay computation by the speed analyzing unit on a display unit. When the speed analyzing unit conducts a delay computation, a delay value of each logic component forming the circuit that is an object of the design is set and altered according to a dullness of a signal waveform inputted to the logic component. The circuit designing apparatus of an interactive type may be applied to a system for conducting a circuit design of an integrated circuit such as an LSI or the like or a printed circuit board.
    Type: Grant
    Filed: January 11, 1999
    Date of Patent: May 29, 2001
    Assignee: Fujitsu Limited
    Inventors: Mitsuru Yasuda, Hiroyuki Sugiyama, Noriyuki Ito, Ryoichi Yamashita, Tadashi Konno, Yasunori Abe, Naomi Bizen, Terunobu Maruyama, Yoshiyuki Kato, Tomoyuki Isomura, Hiroshi Ikeda, Miki Takagi
  • Patent number: 5889677
    Abstract: A circuit designing apparatus of an interactive type which enables a simplified and high-speed circuit design process while largely reducing a burden on a designer, having a speed analyzing unit for conducting a delay computation for each wiring path on a circuit to be designed and a display control unit for displaying a result of the delay computation by the speed analyzing unit on a display unit. When the speed analyzing unit conducts a delay computation, a delay value of each logic component forming the circuit that is an object of the design is set and altered according to a dullness of a signal waveform inputted to the logic component. The circuit designing apparatus of an interactive type may be applied to a system for conducting a circuit design of an integrated circuit such as an LSI or the like or a printed circuit board.
    Type: Grant
    Filed: December 19, 1995
    Date of Patent: March 30, 1999
    Assignee: Fujitsu Limited
    Inventors: Mitsuru Yasuda, Hiroyuki Sugiyama, Noriyuki Ito, Ryoichi Yamashita, Tadashi Konno, Yasunori Abe, Naomi Bizen, Terunobu Maruyama, Yoshiyuki Kato, Tomoyuki Isomura, Hiroshi Ikeda, Miki Takagi
  • Patent number: 5787268
    Abstract: The invention provides an interactive circuit designing apparatus wherein a logic design, a layout design and a speed analysis can cooperate with each other in processing. The interactive circuit designing apparatus comprises a logical designing section for logically designing a design object circuit, a layout designing section for performing mounting arrangement of logical components constituting a design object circuit based on a result of the logical design and performing wiring between the logical components, and a speed analysis section for performing a speed analysis based on calculation of a delay for each of paths on the design object circuit in accordance with a result of the layout. The logical designing section, the layout designing section and the speed analysis section are connected to each other so as to cooperate with each other when necessary. The interactive circuit designing apparatus is applied to an apparatus for designing a circuit of an LSI, a printed circuit board or a like element.
    Type: Grant
    Filed: June 30, 1995
    Date of Patent: July 28, 1998
    Assignee: Fujitsu Limited
    Inventors: Yaroku Sugiyama, Hiroyuki Sugiyama, Noriyuki Ito, Ryouichi Yamashita, Terunobu Maruyama, Yasunori Abe