Patents by Inventor Yasunori Hashimoto

Yasunori Hashimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7718502
    Abstract: A semiconductor apparatus includes a wiring pattern, an insulating film, and a thin-metal-film resistor element. The insulating film is formed on the wiring pattern having connection holes vertically penetrating there-through to expose part of the wiring pattern at bottom regions of the connection holes. The connection holes are arranged with a space there-between. The thin-metal-film resistor element is formed on the insulating film and extending to continuously overlay and contact surfaces of the insulating film, inner walls of the connection holes, and the wiring pattern at the bottom regions of the connection holes.
    Type: Grant
    Filed: November 14, 2007
    Date of Patent: May 18, 2010
    Assignee: Ricoh Company, Ltd.
    Inventors: Kimihiko Yamashita, Yasunori Hashimoto
  • Publication number: 20080100348
    Abstract: A semiconductor device, includes a lower layer side insulation film; a wiring pattern formed on the lower layer side insulation film; a base insulation film formed on the lower layer side insulation film and the wiring pattern; and a plurality of metal thin film resistance elements formed on the base insulation film; wherein a connection hole is formed in the base insulation film on the wiring pattern; the wiring pattern and the metal thin film resistance element are electrically connected in the connection hole; the metal thin film resistance element has a belt shape part arranged separately from the connection hole and a connection part continuously formed with the belt shape part and connected to the wiring pattern in the connection hole; and the connection parts of at least two of the metal thin film resistance element are formed in the single connection hole with a gap in between said connection parts.
    Type: Application
    Filed: September 21, 2006
    Publication date: May 1, 2008
    Inventors: Kimihiko Yamashita, Yasunori Hashimoto
  • Publication number: 20080090371
    Abstract: A semiconductor apparatus includes a wiring pattern, an insulating film, and a thin-metal-film resistor element. The insulating film is formed on the wiring pattern having connection holes vertically penetrating there-through to expose part of the wiring pattern at bottom regions of the connection holes. The connection holes are arranged with a space there-between. The thin-metal-film resistor element is formed on the insulating film and extending to continuously overlay and contact surfaces of the insulating film, inner walls of the connection holes, and the wiring pattern at the bottom regions of the connection holes.
    Type: Application
    Filed: November 14, 2007
    Publication date: April 17, 2008
    Inventors: Kimihiko Yamashita, Yasunori Hashimoto
  • Publication number: 20080079081
    Abstract: A semiconductor apparatus comprises a cell section including at least two transistors. A layer interval insulation coat is formed at least overlying the gate electrode use polysilicon and the gate contact use polysilicon. A source electrode metal coat is formed overlying the semiconductor substrate and insulated from the gate electrode use polysilicon and the gate contact use polysilicon, and is electrically connected to the body diffusion layer and the source diffusion layer. A gate use connection hole is formed on the layer interval insulation coat overlying the gate contact use polysilicon. The gate use connection hole has a width larger than that of the trench. A gate electrode metal coat is formed on the gate use connection hole and the layer interval insulation coat. The polysilicon coat is formed at the same level or lower than the surface of the semiconductor substrate.
    Type: Application
    Filed: September 27, 2007
    Publication date: April 3, 2008
    Inventor: Yasunori Hashimoto
  • Publication number: 20080068047
    Abstract: A disclosed method of producing a semiconductor device includes the steps of (A) forming a gate electrode and a trimming fuse on a semiconductor substrate; (B) forming a side wall insulating film covering the gate electrode and the trimming fuse; (C) forming a conductive film on the side wall insulating film and patterning the conductive film to form an etching stop layer and a resistance element; (D) forming a side wall on the sides of the gate electrode; (E) repeating, one or more times, sub-steps of forming an interlayer insulating film and of forming an upper wiring layer, and then forming a passivation film; (F) removing the passivation film and the interlayer insulating film in the trimming opening forming area until the etching stop layer is exposed; and (G) forming the trimming opening by removing the etching stop layer in the trimming opening forming area.
    Type: Application
    Filed: September 5, 2007
    Publication date: March 20, 2008
    Inventor: Yasunori Hashimoto
  • Patent number: 7312515
    Abstract: A semiconductor apparatus includes a wiring pattern, an insulating film, and a thin-metal-film resistor element. The insulating film is formed on the wiring pattern having connection holes vertically penetrating there-through to expose part of the wiring pattern at bottom regions of the connection holes. The connection holes are arranged with a space there-between. The thin-metal-film resistor element is formed on the insulating film and extending to continuously overlay and contact surfaces of the insulating film, inner walls of the connection holes, and the wiring pattern at the bottom regions of the connection holes.
    Type: Grant
    Filed: June 7, 2004
    Date of Patent: December 25, 2007
    Assignee: Ricoh Company, Ltd.
    Inventors: Kimihiko Yamashita, Yasunori Hashimoto
  • Patent number: 7202549
    Abstract: A semiconductor device, a method for manufacturing the semiconductor device, and an integrated circuit including the semiconductor device are disclosed. The semiconductor device includes a substrate section, a resistor formed on the substrate section, a metal pattern formed on the resistor, an oxide pattern formed on the metal pattern, and a protective film covering the resistor, the metal pattern and the oxide pattern. With this structure, the metal pattern sufficiently prevents formation of an oxide film on a surface of the resistor even when dry ashing or dry etching is performed in the manufacturing process.
    Type: Grant
    Filed: May 19, 2004
    Date of Patent: April 10, 2007
    Assignee: Ricoh Company, Ltd.
    Inventors: Yasunori Hashimoto, Kimihiko Yamashita
  • Publication number: 20060027892
    Abstract: A semiconductor device equipped with a metal thin film resistor is disclosed. The semiconductor device includes a second interlayer insulating film formed on a first interlayer insulating film including a formation area of a wiring pattern. Connecting holes are formed in the second interlayer insulating film corresponding to both ends of the metal thin film resistor and the wiring pattern. An upper part of each connecting hole is formed in a taper shape. A sidewall is formed on the inner wall of each connecting hole. The metal thin film resistor is formed on the second interlayer insulating film between the connecting holes, inside of each connecting hole, and on the wiring pattern.
    Type: Application
    Filed: August 16, 2005
    Publication date: February 9, 2006
    Inventors: Kimihiko Yamashita, Yasunori Hashimoto
  • Publication number: 20050212085
    Abstract: A semiconductor device includes: an insulating film; a metal thin-film resistance element; a wiring pattern formed on the insulating film, a part of which forms an electrode for electrically connecting with the metal thin-film resistance element; and a side wall produced at least on a side surface of the electrode of the wiring pattern, and made of an insulation material, wherein: the metal thin-film resistance element is produced across a top surface of the electrode and a surface of the insulating film via a surface of the side wall.
    Type: Application
    Filed: February 17, 2005
    Publication date: September 29, 2005
    Inventors: Yasunori Hashimoto, Kimihiko Yamashita
  • Publication number: 20040262709
    Abstract: A semiconductor apparatus includes a wiring pattern, an insulating film, and a thin-metal-film resistor element. The insulating film is formed on the wiring pattern having connection holes vertically penetrating there-through to expose part of the wiring pattern at bottom regions of the connection holes. The connection holes are arranged with a space there-between. The thin-metal-film resistor element is formed on the insulating film and extending to continuously overlay and contact surfaces of the insulating film, inner walls of the connection holes, and the wiring pattern at the bottom regions of the connection holes.
    Type: Application
    Filed: June 7, 2004
    Publication date: December 30, 2004
    Inventors: Kimihiko Yamashita, Yasunori Hashimoto
  • Publication number: 20040238920
    Abstract: A semiconductor device, a method for manufacturing the semiconductor device, and an integrated circuit including the semiconductor device are disclosed. The semiconductor device includes a substrate section, a resistor formed on the substrate section, a metal pattern formed on the resistor, an oxide pattern formed on the metal pattern, and a protective film covering the resistor, the metal pattern and the oxide pattern. With this structure, the metal pattern sufficiently prevents formation of an oxide film on a surface of the resistor even when dry ashing or dry etching is performed in the manufacturing process.
    Type: Application
    Filed: May 19, 2004
    Publication date: December 2, 2004
    Inventors: Yasunori Hashimoto, Kimihiko Yamashita
  • Patent number: 6407824
    Abstract: In a color image processing apparatus including a printer unit for printing out image data, it is checked whether the image represented by image data to be processed includes a white region, and image processing is performed while processing to be executed is changed in accordance with the determination result. Upon printing, the printer unit prints out the image data while skipping a region determined as a white region.
    Type: Grant
    Filed: July 21, 1997
    Date of Patent: June 18, 2002
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yasunori Hashimoto
  • Patent number: 6058222
    Abstract: Serial-format image data inputted from a scanner is subjected to scaling processing based upon linear interpolation performed by a linear-interpolation processor. Since the scaling processing is applied to serial-format image data, a line buffer that stores one line of pixels necessitated by the method of linear interpolation need only have a capacity of one main scanning line in the serial format. One main scanning line in the serial format corresponds to the number of elements arrayed in the reading head of a scanner and is sufficiently small in comparison with one line of capacity in a raster format. Image data thus subjected to scaling processing is converted into the raster format by a vertical-horizontal conversion processor and the resulting data is stored in an image memory. Image data read out of the image memory also is subjected to scaling processing after being converted into the serial format.
    Type: Grant
    Filed: March 30, 1995
    Date of Patent: May 2, 2000
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yasunori Hashimoto
  • Patent number: 5867563
    Abstract: A location display apparatus has a display section for displaying a location and voice-synthesizes the location in response to a DTMF signal received from a circuit so as to transmit a corresponding message to the circuit. Moreover, in accordance with received DTMF signals, a power source of the apparatus is controlled, the message is transferred, and the displayed location is changed.
    Type: Grant
    Filed: December 15, 1995
    Date of Patent: February 2, 1999
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masami Kato, Kentaro Matsumoto, Tsunehiro Makino, Yasunori Hashimoto, Hiroyuki Nakanishi, Yasuyuki Nakamura, Atsushi Takahashi
  • Patent number: 5650861
    Abstract: A color image processing apparatus and method through which it is possible to realize high-speed encoding processing of image data containing data indicative of blank spaces. When encoding processing is executed, a CPU sets data, which is added on as a blank space or margin, in a blank-value setting memory, and a DSP for encoding processing reads in the set value before the start of encoding processing, effects a transformation of the color space to undergo encoding processing, and stores the resulting data in its own internal memory, whereby the data stored in the internal memory is used in encoding of blank areas to make possible high-speed encoding processing.
    Type: Grant
    Filed: May 31, 1994
    Date of Patent: July 22, 1997
    Assignee: Canon Kabushiki Kaisha
    Inventors: Toshifumi Nakajima, Yasunori Hashimoto, Yasuyuki Nakamura
  • Patent number: 5424854
    Abstract: An image processing apparatus for half-tone processing input image data having different resolutions by using a dither matrix consisting of a plurality of threshold values is disclosed. The apparatus includes an input device to input image data; a high-resolution dither processing unit to half-tone process the image data of a high resolution; a low-resolution dither processing unit to half-tone process the image data of a low resolution; and a selector to select either one of the two processing units in accordance with the resolution of the input image data. The input device includes a reader to read an original image and generate image data and a resolution conversion processing unit to convert the resolution of the image data obtained by the reader. The high-resolution processing unit uses a spiral-type dither matrix. The low-resolution processing unit uses a dither matrix including a plurality of small spiral-type dither matrices. The input images of different resolutions can be accurately reproduced.
    Type: Grant
    Filed: March 30, 1993
    Date of Patent: June 13, 1995
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yasunori Hashimoto
  • Patent number: 5351137
    Abstract: In a pixel density converting apparatus according to the present invention, a pixel density conversion element for converting a pixel density by a factor of an arbitrary value, such as an element of the projection method or the linear interpolation method, a pixel density conversion element for increasing or decreasing a pixel density by a factor of an integer, such as an element of the majority or logical OR method, and a binarization element for conducting binarization while correcting quantizing errors, such as an element of the error diffusion method or the average error minimizing method, are combined with each other with the advantages and disadvantages of the respective elements taken into consideration, so as to achieve excellent conversion whether or not the image on which pixel density conversion is conducted or an image area is a pseudo half-tone processed image.
    Type: Grant
    Filed: November 30, 1993
    Date of Patent: September 27, 1994
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masami Kato, Takao Kato, Yasunori Hashimoto
  • Patent number: 5321523
    Abstract: An image processing apparatus displaying an identification performance between the image of half-tone and an image of tone other than the half-tone includes a device for correcting the characteristics of the input image signal and an identifying device capable of identifying whether the input image signal is the half-tone image or not without use of the image signal whose characteristics have been corrected. In accordance with the result of the identification performed by this identifying device, an output image signal is selected.
    Type: Grant
    Filed: September 12, 1991
    Date of Patent: June 14, 1994
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yasunori Hashimoto
  • Patent number: 5289293
    Abstract: In a pixel density converting apparatus according to the present invention, a pixel density conversion element for converting a pixel density by a factor of an arbitrary value, such as an element of the projection method or the linear interpolation method, a pixel density conversion element for increasing or decreasing a pixel density by a factor of an integer, such as an element of the majority or logical OR method, and a binarization element for conducting binarization while correcting quantizing errors, such as an element of the error diffusion method or the average error minimizing method, are combined with each other with the advantages and disadvantages of the respective elements taken into consideration, so as to achieve excellent conversion whether or not the image on which pixel density conversion is conducted or an image area is a pseudo half-tone processed image.
    Type: Grant
    Filed: March 12, 1990
    Date of Patent: February 22, 1994
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masami Kato, Takao Kato, Yasunori Hashimoto
  • Patent number: 5245444
    Abstract: Multivalued data enters and is converted into binary (two-valued) data in accordance with plural types of binary-conversion methods. Among the plural types of data obtained by such binary conversion, one is adopted as the object of coding and is coded. The object of coding to be stored in a memory is decided based upon the quantity of coded data.
    Type: Grant
    Filed: March 20, 1991
    Date of Patent: September 14, 1993
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yasunori Hashimoto