Patents by Inventor Yasunori Tanaka

Yasunori Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11810885
    Abstract: A semiconductor element bonding structure capable of strongly bonding a semiconductor element and an object to be bonded and relaxing thermal stress caused by a difference in thermal expansion, by interposing metal particles and Ni between the semiconductor element and the object to be bonded, the metal particles having a lower hardness than Ni and having a micro-sized particle diameter. A plurality of metal particles 5 (aluminum (Al), for example) having a lower hardness than nickel (Ni) and having a micro-sized particle diameter are interposed between a semiconductor chip 3 and a substrate 2 to be bonded to the semiconductor chip 3, and the metal particles 5 are fixedly bonded by the nickel (Ni). Optionally, aluminum (Al) or an aluminum alloy (Al alloy) is used as the metal particles 5, and aluminum (Al) or an aluminum alloy (Al alloy) is used on the surface of the semiconductor chip 3 and/or the surface of the substrate 2.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: November 7, 2023
    Assignee: WASEDA UNIVERSITY
    Inventors: Kohei Tatsumi, Yasunori Tanaka
  • Publication number: 20220219236
    Abstract: Provided are a fine particle production apparatus and a fine particle production method that can control the particle sizes of fine particles, and efficiently produce a large amount of fine particles having good particle size uniformity. The present invention comprises: a raw material supply unit which supplies raw materials for fine particle production into thermal plasma flame; a plasma torch in which the thermal plasma flame is generated, and which evaporates the raw material supplied by the raw material supply unit by means of the thermal plasma flame to form a mixture in a gas phase state; and a plasma generation unit which generates thermal plasma flame inside the plasma torch.
    Type: Application
    Filed: June 4, 2020
    Publication date: July 14, 2022
    Inventors: Yasunori TANAKA, Naoto KODAMA, Kazuki ONDA, Shu WATANABE, Keitaro NAKAMURA, Shiori SUEYASU
  • Publication number: 20220141946
    Abstract: A fine particle manufacturing apparatus and a fine particle manufacturing method are provided. The apparatus includes a raw material supply part supplying a raw material; a plasma torch in which the thermal plasma flame is generated and the raw material supplied by the raw material supply part is vaporized by using the thermal plasma flame to form a mixture in a gas phase state; and a plasma generation part generating the thermal plasma flame inside the plasma torch. The plasma generation part includes a first coil encircling the plasma torch; a second coil encircling the plasma torch and disposed below the first coil; a first power supply part supplying a high-frequency electric current to the first coil; and a second power supply part supplying an amplitude-modulated high-frequency electric current to the second coil. The first coil and the second coil are arranged in the longitudinal direction of the plasma torch.
    Type: Application
    Filed: March 1, 2019
    Publication date: May 5, 2022
    Inventors: Yasunori TANAKA, Naoto KODAMA, Kazuki ONDA, Shu WATANABE, Keitaroh NAKAMURA, Shiori SUEYASU, Tomoya WATANABE
  • Patent number: 11198957
    Abstract: A fabric for arc-protective garments includes first yarns and second yarns different from the first yarns. The first yarns include first modacrylic fibers, and the first modacrylic fibers contain an infrared absorber in an amount of 2.5 wt % or more with respect to a total weight of the first modacrylic fibers. The weight of the infrared absorber per unit area in the fabric for arc-protective garments is 0.05 oz/yd2 or more. An arc-protective garment includes the fabric for arc-protective garments.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: December 14, 2021
    Assignee: KANEKA CORPORATION
    Inventors: Motohiro Sato, Yoshitomo Matsumoto, Tatsuro Ohzeki, Wataru Mio, Yasunori Tanaka, Yuto Utsunomiya, Tomoya Matsushima
  • Publication number: 20210316268
    Abstract: Provided are a fine particle manufacturing apparatus and a fine particle manufacturing method, which manufacture smaller fine particles. The fine particle manufacturing apparatus has: a raw material supply unit that supplies raw materials for producing fine particles into a thermal plasma flame; a plasma torch in which the thermal plasma flame is generated and the raw materials supplied by the raw material supply unit is evaporated by the thermal plasma flame to form a mixture in a gaseous state; a plasma generation unit that generates the thermal plasma flame inside the plasma torch; and a gas supply unit that supplies quenched gas to the thermal plasma flame, wherein the gas supply unit supplies the quenched gas with time modulation of the supply amount of the quenched gas.
    Type: Application
    Filed: September 2, 2019
    Publication date: October 14, 2021
    Inventors: Yasunori TANAKA, Kotaro SHIMIZU, Shiori SUEYASU, Shu WATANABE, Tomoya WATANABE, Keitaro NAKAMURA
  • Publication number: 20210225794
    Abstract: A semiconductor element bonding structure capable of strongly bonding a semiconductor element and an object to be bonded and relaxing thermal stress caused by a difference in thermal expansion, by interposing metal particles and Ni between the semiconductor element and the object to be bonded, the metal particles having a lower hardness than Ni and having a micro-sized particle diameter. A plurality of metal particles 5 (aluminum (Al), for example) having a lower hardness than nickel (Ni) and having a micro-sized particle diameter are interposed between a semiconductor chip 3 and a substrate 2 to be bonded to the semiconductor chip 3, and the metal particles 5 are fixedly bonded by the nickel (Ni). Optionally, aluminum (Al) or an aluminum alloy (Al alloy) is used as the metal particles 5, and aluminum (Al) or an aluminum alloy (Al alloy) is used on the surface of the semiconductor chip 3 and/or the surface of the substrate 2.
    Type: Application
    Filed: February 26, 2021
    Publication date: July 22, 2021
    Inventors: Kohei Tatsumi, Yasunori Tanaka
  • Publication number: 20210061665
    Abstract: Provided are a method and apparatus capable of producing fine particles with favorable particle size distribution. In a production method in which feedstock for fine particle production is supplied intermittently into a modulated induction thermal plasma flame, the feedstock is vaporized to form a gas phase mixture, and the mixture is cooled to produce the fine particles: a modulated induction thermal plasma flame in which the temperature state is time-modulated is generated; the modulated induction thermal plasma flame is switched between a high temperature state and a low temperature state; and when the modulated induction thermal plasma flame is in the high temperature state, the feedstock is supplied together with a carrier gas, and when the modulated induction thermal plasma flame is in the low temperature state, supply of the feedstock is suspended and a gas of the same type as the carrier gas is supplied.
    Type: Application
    Filed: May 8, 2019
    Publication date: March 4, 2021
    Inventors: Yasunori TANAKA, Naoto KODAMA, Yousuke ISHISAKA, Shu WATANABE, Keitaro NAKAMURA, Shiori SUEYASU
  • Publication number: 20210045269
    Abstract: The present invention provides an electromagnetic wave absorbing sheet which contains conductive short fibers and an insulating material, and which exhibits particularly high radio wave absorbing properties in one direction.
    Type: Application
    Filed: January 29, 2019
    Publication date: February 11, 2021
    Applicant: DUPONT TEIJIN ADVANCED PAPERS (JAPAN), LTD.
    Inventors: Shinji NARUSE, Tatsushi FUJIMORI, Koichi UKIGAYA, Yasunori TANAKA
  • Publication number: 20210029854
    Abstract: The present invention provides an electromagnetic wave absorbing sheet which contains: conductive short fibers; and soft magnetic particles, each of which is covered by an insulating material.
    Type: Application
    Filed: January 29, 2019
    Publication date: January 28, 2021
    Applicant: DUPONT TEIJIN ADVANCED PAPERS (JAPAN), LTD.
    Inventors: Shinji NARUSE, Tatsushi FUJIMORI, Koichi UKIGAYA, Yasunori TANAKA
  • Patent number: 10836112
    Abstract: Provided is a method for producing a laminate, comprising laminating an aramid paper sheet and a polyimide film together by performing heating and pressurizing process under conditions of a temperature of 275 to 320° C. and a pressure of 50 to 400 kgf/cm. In the present invention, an aramid paper sheet-polyimide film laminate with excellent heat resistance, electrical properties, chemical resistance, mechanical properties, and the like can be manufactured by laminating the aramid paper sheet and the polyimide film in a simple method without impairing their properties.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: November 17, 2020
    Assignee: DUPONT TEIJIN ADVANCED PAPERS (JAPAN), LTD.
    Inventors: Koichi Ukigaya, Tatsushi Fujimori, Shinji Naruse, Chihiro Kondo, Yasunori Tanaka
  • Patent number: 10654247
    Abstract: The present invention provides an electromagnetic wave suppression sheet provided with: an absorption layer which has surface resistivity of at least 100?/? and which contains an electrical conductive material and an insulating material in the state where the electrical conductive material and the insulating material are in direct contact with each other, the insulating material having a dielectric loss tangent of 0.01 or larger at a frequency of 60 Hz at 20° C.; and a contact layer which is formed on a surface, of the absorption layer, opposite to a surface to be irradiated with electromagnetic waves and of which a surface in contact with the absorption layer has surface resistivity of at least 20?/?.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: May 19, 2020
    Assignee: DUPONT TEIJIN ADVANCED PAPERS (JAPAN), LTD.
    Inventors: Shinji Naruse, Tatsushi Fujimori, Koichi Ukigaya, Chihiro Kondo, Yasunori Tanaka
  • Patent number: 10577724
    Abstract: An arc resistant acrylic fiber includes an acrylic polymer. The arc resistant acrylic fiber also includes an infrared absorber in an amount of 1 wt % to 30 wt % with respect to a total weight of the acrylic polymer.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: March 3, 2020
    Assignee: KANEKA CORPORATION
    Inventors: Tatsuro Ohzeki, Keita Uchibori, Wataru Mio, Yasunori Tanaka, Yuto Utsunomiya
  • Publication number: 20200061966
    Abstract: The present invention provides an electromagnetic wave suppression sheet provided with: an absorption layer which has surface resistivity of at least 100 ?/? and which contains an electrical conductive material and an insulating material in the state where the electrical conductive material and the insulating material are in direct contact with each other, the insulating material having a dielectric loss tangent of 0.01 or larger at a frequency of 60 Hz at 20° C.; and a contact layer which is formed on a surface, of the absorption layer, opposite to a surface to be irradiated with electromagnetic waves and of which a surface in contact with the absorption layer has surface resistivity of at least 20 ?/?.
    Type: Application
    Filed: November 20, 2017
    Publication date: February 27, 2020
    Applicant: DUPONT TEIJIN ADVANCED PAPERS (JAPAN), LTD.
    Inventors: Shinji NARUSE, Tatsushi FUJIMORI, Koichi UKIGAYA, Chihiro KONDO, Yasunori TANAKA
  • Patent number: 10418477
    Abstract: A silicon carbide semiconductor device, including a silicon carbide substrate, a drift layer provided on a front surface of the silicon carbide substrate, an embedded layer selectively provided in a surface layer of the drift layer, an epitaxial layer provided on the drift layer, a channel layer provided on the epitaxial layer, a source region selectively provided in a surface layer of the channel layer, a trench penetrating the source region and the channel layer and reaching the epitaxial layer, a gate electrode provided in the trench via a gate insulating film, a source electrode in contact with the channel layer and the source region, and a drain electrode provided on a rear surface of the silicon carbide substrate. The embedded layer is arranged underneath the trench in a depth direction. A longitudinal direction of the trench, which is perpendicular to the depth direction, is parallel to the off-direction of the silicon carbide substrate.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: September 17, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takeshi Tawara, Akimasa Kinoshita, Shinsuke Harada, Yasunori Tanaka
  • Patent number: 10403713
    Abstract: In a first main surface of a silicon carbide semiconductor base, a trench is formed. On a first main surface side of the silicon carbide semiconductor base, an n-type silicon carbide epitaxial layer is deposited. In a surface of the n-type silicon carbide epitaxial layer, an n-type high-concentration region is provided. In the surface of the n-type silicon carbide epitaxial layer, a first p-type base region and a second p+-type base region are selectively provided. The second p+-type base region is formed at the bottom of the trench. A depth of the n-type high-concentration region is deeper than that of the first p-type base region and the second p+-type base region. Thus, by an easy method, the electric field at a gate insulating film at the bottom of the trench is mitigated, enabling the breakdown voltage of the active region to be maintained and the ON resistance to be lowered.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: September 3, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Masanobu Iwaya, Akimasa Kinoshita, Shinsuke Harada, Yasunori Tanaka
  • Patent number: 10403749
    Abstract: In a first main surface side of a silicon carbide semiconductor base, a trench is formed. A second base region of a second conductivity type is arranged at a position facing the trench in a depth direction. An end (toward a drain electrode) of the second base region of the second conductivity type, and an end (toward the drain electrode) of a first base region of the second conductivity type reach a position deeper than an end (toward the drain electrode) of a region of a first conductivity type. Thus, the electric field at a gate insulating film at the trench bottom is mitigated, suppressing the breakdown voltage of the active region and enabling breakdown voltage design of the edge termination region to be facilitated. Further, such a semiconductor device may be formed by an easy method of manufacturing.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: September 3, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Akimasa Kinoshita, Shinsuke Harada, Yasunori Tanaka
  • Publication number: 20190206985
    Abstract: In a first main surface of a silicon carbide semiconductor base, a trench is formed. On a first main surface side of the silicon carbide semiconductor base, an n-type silicon carbide epitaxial layer is deposited. In a surface of the n-type silicon carbide epitaxial layer, an n-type high-concentration region is provided. In the surface of the n-type silicon carbide epitaxial layer, a first p-type base region and a second p+-type base region are selectively provided. The second p+-type base region is formed at the bottom of the trench. A depth of the n-type high-concentration region is deeper than that of the first p-type base region and the second p+-type base region. Thus, by an easy method, the electric field at a gate insulating film at the bottom of the trench is mitigated, enabling the breakdown voltage of the active region to be maintained and the ON resistance to be lowered.
    Type: Application
    Filed: March 6, 2019
    Publication date: July 4, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Masanobu IWAYA, Akimasa KINOSHITA, Shinsuke HARADA, Yasunori TANAKA
  • Publication number: 20190165166
    Abstract: In a first main surface side of a silicon carbide semiconductor base, a trench is formed. A second base region of a second conductivity type is arranged at a position facing the trench in a depth direction. An end (toward a drain electrode) of the second base region of the second conductivity type, and an end (toward the drain electrode) of a first base region of the second conductivity type reach a position deeper than an end (toward the drain electrode) of a region of a first conductivity type. Thus, the electric field at a gate insulating film at the trench bottom is mitigated, suppressing the breakdown voltage of the active region and enabling breakdown voltage design of the edge termination region to be facilitated. Further, such a semiconductor device may be formed by an easy method of manufacturing.
    Type: Application
    Filed: January 31, 2019
    Publication date: May 30, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Akimasa KINOSHITA, Shinsuke HARADA, Yasunori TANAKA
  • Patent number: 10276653
    Abstract: In a first main surface of a silicon carbide semiconductor base, a trench is formed. On a first main surface side of the silicon carbide semiconductor base, an n-type silicon carbide epitaxial layer is deposited. In a surface of the n-type silicon carbide epitaxial layer, an n-type high-concentration region is provided. In the surface of the n-type silicon carbide epitaxial layer, a first p-type base region and a second p+-type base region are selectively provided. The second p+-type base region is formed at the bottom of the trench. A depth of the n-type high-concentration region is deeper than that of the first p-type base region and the second p+-type base region. Thus, by an easy method, the electric field at a gate insulating film at the bottom of the trench is mitigated, enabling the breakdown voltage of the active region to be maintained and the ON resistance to be lowered.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: April 30, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Masanobu Iwaya, Akimasa Kinoshita, Shinsuke Harada, Yasunori Tanaka
  • Publication number: 20190061270
    Abstract: Provided is a method for producing a laminate, comprising laminating an aramid paper sheet and a polyimide film together by performing heating and pressurizing process under conditions of a temperature of 275 to 320° C. and a pressure of 50 to 400 kgf/cm. In the present invention, an aramid paper sheet-polyimide film laminate with excellent heat resistance, electrical properties, chemical resistance, mechanical properties, and the like can be manufactured by laminating the aramid paper sheet and the polyimide film in a simple method without impairing their properties.
    Type: Application
    Filed: February 8, 2017
    Publication date: February 28, 2019
    Applicant: DUPONT TEIJIN ADVANCED PAPERS (JAPAN), LTD.
    Inventors: Koichi UKIGAYA, Tatsushi FUJIMORI, Shinji NARUSE, Chihiro KONDO, Yasunori TANAKA