Patents by Inventor Yasuo Kominami

Yasuo Kominami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210293942
    Abstract: A method of calculating distance-correction data performed by a range-finding device includes: emitting light to a calibration target at a specified distance from a range-finding device and receiving light reflected from the calibration target that has been irradiated with the emitted light, with an optical-transmission member between the range-finding device and the calibration target, to obtain an actual-measured distance from the range-finding device to the calibration target; and calculating distance-correction data using actual-measurement error data between the specified distance and the actual measured distance to the calibration target, the distance-correction data being used to correct a distance from the range-finding device to a target object measured by emitting light to the target object and receiving light reflected from the target object that has been irradiated with the emitted light, with the optical-transmission member between the range-finding device and the target object.
    Type: Application
    Filed: March 18, 2021
    Publication date: September 23, 2021
    Inventors: Toshiyuki KAWASAKI, Shunsuke MURAMOTO, Yasuo KOMINAMI, Shinji NOGUCHI
  • Patent number: 4942536
    Abstract: In a case where an electronic circuit having the same function is to be realized by a different device, it is indispensable to prepare circuit diagrams conforming to devices and to utilize them for the job of circuit simulation or chip layout. When the circuit diagrams are to be automatically translated for the above purpose, translation rules become different depending upon the connective relations of an element to be translated, with other elements in the circuit or upon a function performed by the element. The present invention puts the rules into knowledge from the viewpoint of knowledge engineering and utilizes it thereby to realize the intended purpose.
    Type: Grant
    Filed: April 21, 1986
    Date of Patent: July 17, 1990
    Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering Ltd.
    Inventors: Toshinori Watanabe, Fumihiko Mori, Tamotsu Nishiyama, Makoto Furihata, Yasuo Kominami, Noboru Horie
  • Patent number: 4803636
    Abstract: In order to translate an original circuit consisting of a set of first devices into a target circuit which consists of a set of second devices different from the first devices, and which has the same functions as the original circuit, provision is made of memory means for storing translation rules in the first devices, translation rules in the second devices, and translation rules between the first devices and the second devices, and translation means which successively refers to these translation rules and translates the original circuit data into the target circuit data via steps that translate the original circuit data into a plurality of intermediate data.
    Type: Grant
    Filed: September 25, 1986
    Date of Patent: February 7, 1989
    Assignees: Hitachi Ltd., Hitachi Micro Computer Eng. Ltd.
    Inventors: Tamotsu Nishiyama, Toshinori Watanabe, Noboru Horie, Makoto Furihata, Yasuo Kominami, Fumihiko Mori
  • Patent number: 4525636
    Abstract: A variable electronic impedance circuit contains a voltage-current converter having an input terminal which is supplied with an input signal voltage, and a variable-gain current amplifier having an input terminal which is supplied with an output current of the voltage-current converter. The output signal current of the amplifier is fed back to the input terminal of the voltage-current converter.In order to prevent undesirable oscillation immediately after the closure of a power supply switch, the variable electronic impedance circuit includes a control circuit which substantially inhibits the operation of the voltage-current converter for a predetermined time after the closure of the power supply switch.
    Type: Grant
    Filed: August 30, 1982
    Date of Patent: June 25, 1985
    Assignees: Hitachi, Ltd., Pioneer Electronic Corp.
    Inventors: Yasuo Kominami, Yuichi Ohkubo, Kohki Aizawa, Satoshi Sasaki
  • Patent number: 4510458
    Abstract: An amplifier circuit has an operational amplifier and a negative feedback circuit. An input signal is applied to the non-inverting input terminal of the operational amplifier, whereby a first output signal is provided from the output terminal of the operational amplifier. The first output signal is fed back to the inverting input terminal of the operational amplifier through the negative feedback circuit. The negative feedback signal of the negative feedback circuit is fed back to the inverting input terminal through an impedance converter. Thus, a second output signal of low distortion factor is derived from the output terminal of the impedance converter.
    Type: Grant
    Filed: August 18, 1982
    Date of Patent: April 9, 1985
    Assignees: Hitachi, Ltd., Pioneer Electronic Corp.
    Inventors: Tetsuo Sato, Yasuo Kominami, Yoshiyuki Takizawa, Akira Haeno
  • Patent number: 4500932
    Abstract: A signal processing circuit which can be used, for example, as a playback equalizer is formed in a semiconductor integrated circuit with a main path and a side path arrayed between the input terminal and the output terminal of the integrated circuit. The signals at the ends of the main and side paths are added together to obtain the output signal for the signal processor. A filter in the main path determines its frequency characteristics. On the other hand, a variable gain control means having substantially flat frequency characteristics is inserted in the side path and its gain can be changed in response to control data to control the output signal of the signal processor.
    Type: Grant
    Filed: June 3, 1982
    Date of Patent: February 19, 1985
    Assignee: Hitachi, Ltd.
    Inventors: Tetsuo Sato, Yasuo Kominami
  • Patent number: 4476502
    Abstract: A noise reduction system is provided which can operate as either a Dolby B-type or C-type system. In either case, an input signal is applied to the variable impedance of a high-level side chain through an identical shared filter circuit network. The high-level side chain has two voltage-current converters for controlling the variable impedance. By substantially inhibiting the operation of one of the two converters, the system operates as a C-type Dolby system. On the other hand, when the system operates as a B-type Dolby system, a bias current is applied to each of the two converters during periods of no input signal. This bias current is about half of a minute bias control current which is applied during no signal periods to the single converter used when the system operates as the C-type Dolby system.
    Type: Grant
    Filed: August 27, 1982
    Date of Patent: October 9, 1984
    Assignees: Hitachi, Ltd., Pioneer Electronic Corporation
    Inventors: Kazuo Watanabe, Yasuo Kominami, Yoshiyuki Takizawa, Akira Haeno
  • Patent number: 4473852
    Abstract: Conventional Dolby B-type or C-type noise reduction systems respond sensitively to an A.C. bias signal during recording onto a magnetic tape. As a result, the system might exhibit a large encode error. In order to reduce such encode error, the gain - frequency characteristic control sensitivity of a side chain in the system to the A.C. bias signal to be supplied to a recording head is set at a value smaller than that of the gain - frequency characteristic control sensitivity of the side chain to an encode input signal at an audio frequency. Such a reduction of the encode error is achieved by connecting a bias trap circuit to a gain control amplifier included in the side chain.
    Type: Grant
    Filed: August 27, 1982
    Date of Patent: September 25, 1984
    Assignees: Hitachi, Ltd., Pioneer Electronic Corporation
    Inventors: Yasuo Kominami, Kazuo Watanabe, Fumihiko Yokogawa, Nobuhiro Suzuki
  • Patent number: 4412189
    Abstract: Either an input signal of a combining network or an output signal of an inverter arranged on a main path is fed to a side path through a mode switch in a switchable signal compressor/signal expander. Since an input terminal of a control amplifier is connected to a variable filter without passing through a signal amplifier, the deviation of the detection characteristic of a rectifier and integrator attributed to D.C. offset voltages of the signal amplifier and the control amplifier can be reduced. On the other hand, a switchable signal compressor/signal expander in another aspect of performance has a reference voltage generator for producing a D.C. reference voltage, and the output D.C. level of the control amplifier is maintained at a level approximate to the D.C. reference voltage. The other ends of first and second capacitors of the rectifier and integrator are also supplied with the D.C.
    Type: Grant
    Filed: May 12, 1981
    Date of Patent: October 25, 1983
    Assignee: Hitachi, Ltd.
    Inventors: Yasuo Kominami, Tetsuo Sato, Yuichi Ohkubo
  • Patent number: 4362998
    Abstract: An FM detector is constructed of a phase shift network and an analog multiplier. The analog multiplier includes a differential amplifier circuit and a phase detector circuit. The differential amplifier circuit includes differential pair transistors which are driven by FM intermediate frequency signals. One of the differential pair transistors has another transistor connected thereto which is also driven by the FM intermediate frequency signal. A collector signal of either one of the differential pair transistors is applied to the phase detector circuit through the phase shift network, while a collector signal of the other transistor is directly applied to the phase detector circuit. An emitter of the one transistor and an emitter of the other transistor are connected through resistors, whereby the signal-to-noise ratio of the FM detector is improved.
    Type: Grant
    Filed: January 31, 1979
    Date of Patent: December 7, 1982
    Assignee: Hitachi, Ltd.
    Inventors: Kazuo Watanabe, Masanori Ienaka, Yasuo Kominami, Makoto Homma
  • Patent number: 4354209
    Abstract: A recording/playing circuit includes a noise reduction circuit, a switching circuit and a control circuit. The noise reduction circuit includes a pre-amplifier, a combining network, an inverter circuit and a side chain. The switching circuit has first, second and third input positions and an output terminal. The first input position is coupled to the output of the pre-amplifier, the second input position is coupled to the output of the inverter circuit, and the output terminal is coupled to the side chain. The third input position is connected to a muting circuit. The control circuit controls the switching circuit so that one of the electric signals applied to the first, second and third input positions of the switching circuit may be selectively transmitted to the output terminal of the switching circuit.
    Type: Grant
    Filed: February 3, 1981
    Date of Patent: October 12, 1982
    Assignee: Hitachi, Ltd.
    Inventors: Tetsuo Sato, Yasuo Kominami
  • Patent number: 4313145
    Abstract: An output from an OCL type power output circuit is applied to a loudspeaker load through a switching means such as a relay. A first detector circuit and a second detector circuit detect a first operating status (e.g., output d.c. level) and a second operating status (e.g., output current level of an output transistor) of the OCL type power output circuit, respectively. The detection output signals of the first detector circuit and the second detector circuit are respectively applied to a first detecting transistor and a second detecting transistor. In the normal operation status of the OCL type power output circuit, the first detecting transistor and the second detecting transistor are respectively biased into "on" states by the first detector circuit and the second detector circuit so as to permit predetermined currents to flow. When the first and second detecting transistors are in their "on" states they control a driving transistor into an "on" state.
    Type: Grant
    Filed: October 11, 1979
    Date of Patent: January 26, 1982
    Assignee: Hitachi, Ltd.
    Inventors: Masanori Ienaka, Masahiro Yamamura, Kazuo Watanabe, Yasuo Kominami
  • Patent number: 4297601
    Abstract: A monostable multivibrator circuit is disclosed. It is characterized by comprising a time constant circuit which includes a capacitor, an amplifier circuit which receives an output signal of the time constant circuit and in which a signal amplifying transistor operates in the non-saturated state, a positive feedback circuit which is connected between the output end of the amplifier circuit and the input end of the time constant circuit and in which a signal amplifying transistor operates in the non-saturated state, and a trigger terminal which is disposed in a circuit loop constructed of the time constant circuit, the amplifier circuit and the positive feedback circuit. Further, it is characterized in that a signal which is produced by the shift from the non-conductive state to the conductive state of the signal amplifying transistor connected to an output terminal of the positive feedback circuit is supplied to the time constant circuit as a positive feedback signal.
    Type: Grant
    Filed: January 16, 1979
    Date of Patent: October 27, 1981
    Assignees: Hitachi, Ltd., Trio Kabushiki Kaisha
    Inventors: Takeshi Wada, Yasuo Kominami, Yukihiko Miyamoto, Tsuneo Yamada
  • Patent number: 4292549
    Abstract: A monostable multivibrator circuit including a time constant circuit which includes a capacitor, an amplifier circuit which receives an output signal of the time constant circuit, and a positive feedback circuit which is connected between an output end of the amplifier circuit and an input end of the time constant circuit, characterized in that a trigger circuit is incorporated in a part of a circuit loop which is constructed of the time constant circuit, the amplifier circuit and the positive feedback circuit, the trigger circuit comprising an emitter-follower transistor which receives a feedback signal, another emitter-follower transistor which receives a trigger signal and whose emitter is connected to an emitter of the first-mentioned emitter-follower transistor in common, and a constant-current circuit which supplies a constant current to the emitters connected in common.
    Type: Grant
    Filed: January 12, 1979
    Date of Patent: September 29, 1981
    Assignees: Hitachi Ltd., Trio Kabushiki Kaisha
    Inventors: Takeshi Wada, Masanori Ienaka, Yasuo Kominami, Yukihiko Miyamoto, Tsuneo Yamada
  • Patent number: 4283674
    Abstract: This invention relates to a constant voltage output circuit using, as its reference potential source, power source feed terminals for feeding a power source voltage to a reference potential source of a given circuit. The constant voltage output circuit includes a series circuit of an npn transistor and a pnp transistor interposed between the reference potential source of the given circuit and the power source feed terminals, means for biasing the base potential of the pnp transistor by a predetermined potential with respect to the potential of the power source feed terminals, and an emitter follower circuit disposed in the collector output circuit of the npn transistor of the series circuit, and forming a negative feed-back circuit.
    Type: Grant
    Filed: July 19, 1979
    Date of Patent: August 11, 1981
    Assignees: Hitachi, Ltd., Pioneer Electronic Corp.
    Inventors: Yasuo Kominami, Masahiro Yamamura, Katsuji Mizumoto, Toshihide Hanada
  • Patent number: 4282448
    Abstract: This invention discloses a monostable multivibrator which is useful for an FM detector circuit of a pulse count system. The monostable multivibrator has a time constant circuit which includes a capacitor, an amplifier circuit which receives an output of the time constant circuit, a positive feedback circuit which is connected between an output end of the amplifier circuit and an input end of the time constant circuit, and a trigger terminal which is disposed in a circuit loop constructed of the time constant circuit, the amplifier circuit and the positive feedback circuit; and is characterized in that the amplifier circuit is a differential amplifier which is made up of a pair of transistors connected in the differential form, the transistors being connected in common through emitter resistances connected in series with respective emitters thereof. Thus, the monostable multivibrator can provide pulse signals of a fixed pulse width without being influenced by noise.
    Type: Grant
    Filed: December 13, 1978
    Date of Patent: August 4, 1981
    Assignees: Hitachi, Ltd., Trio Kabushiki Kaisha
    Inventors: Takeshi Wada, Masanori Ienaka, Yasuo Kominami, Yukihiko Miyamoto, Tsuneo Yamada
  • Patent number: 4276442
    Abstract: The output derived from an electric circuit such as an OCL type power amplifier circuit is delivered to a load such as a speaker, through a switching means such as a relay. When the operation of the electric circuit has come out of a predetermined range of operation, the switching means is operated to break the connection between the electric circuit and the load. A detection circuit for detecting the operation of the electric circuit includes a detecting transistor constructed in a semiconductor integrated circuit. The detecting transistor is connected at its base to the input terminal for external connection of the semiconductor integrated circuit, so as to receive a signal representative of the operation state of the electric circuit. The detecting transistor is so biased as to allow a predetermined electric current to flow therethrough, when the electric circuit is operating within the predetermined range of operation.
    Type: Grant
    Filed: March 29, 1979
    Date of Patent: June 30, 1981
    Assignee: Hitachi, Ltd.
    Inventors: Masanori Ienaka, Masahiro Yamamura, Kazuo Watanabe, Yasuo Kominami
  • Patent number: 4272709
    Abstract: The present invention is related to a temperature-compensated circuit for controlling the drive of a motor, comprising a differential comparator for comparing a running-speed signal of a motor with a reference signal, and a feedback amplifier having a differential amplifier to which is given an input offset.
    Type: Grant
    Filed: July 18, 1979
    Date of Patent: June 9, 1981
    Assignees: Pioneer Electronic Corporation, Hitachi, Ltd.
    Inventors: Katsuji Mizumoto, Toshihide Hanada, Yasuo Kominami, Masahiro Yamamura
  • Patent number: 4264873
    Abstract: A differential amplification is disclosed which comprises differential paired transistors. The direct bias current flowing in the differential paired transistors is determined by a constant current flowing from a first constant current circuit connected to the emitters of the differential paired transistors. The collector current of one of the differential paired transistors is caused to flow as an input current in a high-precision current mirror circuit. The current value of the constant current flowing in the first constant current circuit is set at 2Io. Since a direct base current Ib flows in the differential paired transistors, the current value of the collector current of one of the differential paired transistors is (Io-Ib). Accordingly, the high-precision current mirror circuit generates an output current of a current value of (Io-Ib) at the output terminal thereof.
    Type: Grant
    Filed: July 10, 1979
    Date of Patent: April 28, 1981
    Assignees: Hitachi, Ltd., Pioneer Electronic Corporation
    Inventors: Yasuo Kominami, Masahiro Yamamura, Katsuji Mizumoto, Toshihide Hanada
  • Patent number: 4247949
    Abstract: An input signal is applied to a first limiting amplifier circuit, and an output of the first limiting amplifier circuit is applied to a second limiting amplifier circuit. An output of the second limiting amplifier circuit is applied to a third limiting amplifier circuit. The output signal of the first limiting amplifier circuit is applied to a first detector circuit, the output signal of the second limiting amplifier circuit is applied to a second detector circuit, and the output signal of the third limiting amplifier circuit is applied to a third detector circuit. Bias means for stipulating the bias states of the first, second and third detector circuits are coupled to the third detector circuit. An output signal of the third detector circuit is applied to the second detector circuit as a bias signal, and an output signal of the second detector circuit is applied to the first detector circuit as a bias signal.
    Type: Grant
    Filed: February 6, 1979
    Date of Patent: January 27, 1981
    Assignee: Hitachi, Ltd.
    Inventors: Kazuo Watanabe, Masanori Ienaka, Yasuo Kominami, Makoto Homma