Patents by Inventor Yasuo Matsumiya
Yasuo Matsumiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11323636Abstract: A control circuit for infrared detectors, includes: a driving circuit configured to drive a plurality of infrared detectors and generates, for each frame, a signal according to infrared rays incident on the plurality of infrared detectors; a holding circuit configured to hold a first signal generated by the driving circuit in a first frame and a second signal generated by the driving circuit in a second frame before the first frame; a difference calculation circuit configured to calculate a difference between the first signal and the second signal; and an amplifier circuit configured to amplify and output the difference calculated by the difference calculation circuit.Type: GrantFiled: October 21, 2019Date of Patent: May 3, 2022Assignee: FUJITSU LIMITEDInventor: Yasuo Matsumiya
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Patent number: 11323641Abstract: A control method of an infrared detector, for obtaining a wider dynamic range and preventing an over-range, is disclosed. The method includes: monitoring a value acquired in response to an electric current flowing in each of a plurality of infrared detection elements configuring the infrared detector, and lowering, when the value acquired in response to the electric current flowing in the infrared detection element reaches a threshold value within a detection time, sensitivity of the infrared detection element within the detection time.Type: GrantFiled: June 28, 2019Date of Patent: May 3, 2022Assignee: FUJITSU LIMITEDInventor: Yasuo Matsumiya
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Patent number: 10904459Abstract: An array sensor includes a sensor element array that includes a plurality of sensor elements, a signal processing circuit array that includes a plurality of signal processing circuits coupled to the corresponding sensor elements, and a resistor network that supplies bias voltages to the corresponding signal processing circuits, wherein different voltages are applied to at least two voltage application nodes in the resistor network.Type: GrantFiled: July 20, 2018Date of Patent: January 26, 2021Assignee: FUJITSU LIMITEDInventor: Yasuo Matsumiya
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Publication number: 20200154062Abstract: A control circuit for infrared detectors, includes: a driving circuit configured to drive a plurality of infrared detectors and generates, for each frame, a signal according to infrared rays incident on the plurality of infrared detectors; a holding circuit configured to hold a first signal generated by the driving circuit in a first frame and a second signal generated by the driving circuit in a second frame before the first frame; a difference calculation circuit configured to calculate a difference between the first signal and the second signal; and an amplifier circuit configured to amplify and output the difference calculated by the difference calculation circuit.Type: ApplicationFiled: October 21, 2019Publication date: May 14, 2020Applicant: FUJITSU LIMITEDInventor: Yasuo MATSUMIYA
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Patent number: 10616517Abstract: An imaging apparatus includes an image sensor including a common sensor element, the common sensor element having a plurality of output systems therefrom, and a signal processing circuit that generates an image signal from outputs of the image sensor, wherein the plurality of output systems individually include a transistor, a capacitor that stores charge in accordance with a current flowing through the sensor element via the transistor, and output circuitry that outputs a sensor signal in accordance with a voltage of the capacitor, wherein the transistors individually allow the current to flow in time periods different with each other, and the signal processing circuit does not use the sensor signals if the sensor signals do not match with each other, and the signal processing circuit uses the sensor signals for generating the image signal if the sensor signals match with each other.Type: GrantFiled: July 10, 2017Date of Patent: April 7, 2020Assignee: FUJITSU LIMITEDInventors: Hironori Nishino, Yasuo Matsumiya
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Publication number: 20200018653Abstract: A control method of an infrared detector, for obtaining a wider dynamic range and preventing an over-range, is disclosed. The method includes: monitoring a value acquired in response to an electric current flowing in each of a plurality of infrared detection elements configuring the infrared detector, and lowering, when the value acquired in response to the electric current flowing in the infrared detection element reaches a threshold value within a detection time, sensitivity of the infrared detection element within the detection time.Type: ApplicationFiled: June 28, 2019Publication date: January 16, 2020Applicant: FUJITSU LIMITEDInventor: Yasuo MATSUMIYA
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Publication number: 20190037153Abstract: An array sensor includes a sensor element array that includes a plurality of sensor elements, a signal processing circuit array that includes a plurality of signal processing circuits coupled to the corresponding sensor elements, and a resistor network that supplies bias voltages to the corresponding signal processing circuits, wherein different voltages are applied to at least two voltage application nodes in the resistor network.Type: ApplicationFiled: July 20, 2018Publication date: January 31, 2019Applicant: FUJITSU LIMITEDInventor: Yasuo MATSUMIYA
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Patent number: 10145741Abstract: A heat source detection device includes a processor configured to calculate, as a single-wavelength temperature, one of a first temperature obtained by converting a first output output from the infrared sensor in accordance with an incident amount of infrared rays in a first infrared wavelength band into a temperature, a second temperature obtained by converting a second output from the infrared sensor in accordance with an incident amount of infrared rays in a second infrared wavelength band into a temperature and an average value of the first and second temperatures, and calculate a dual-wavelength temperature obtained by converting the ratio between the first and second outputs into a temperature; and to determine a temperature of the heat source based on the dual-wavelength temperature and determine a distance to the heat source from the infrared sensor based on a comparison result between the single-wavelength temperature and dual-wavelength temperature.Type: GrantFiled: May 31, 2017Date of Patent: December 4, 2018Assignee: FUJITSU LIMITEDInventors: Hironori Nishino, Yasuo Matsumiya
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Publication number: 20180031425Abstract: A heat source detection device includes a processor configured to calculate, as a single-wavelength temperature, one of a first temperature obtained by converting a first output output from the infrared sensor in accordance with an incident amount of infrared rays in a first infrared wavelength band into a temperature, a second temperature obtained by converting a second output output from the infrared sensor in accordance with an incident amount of infrared rays in a second infrared wavelength band into a temperature and an average value of the first and second temperatures, and calculate a dual-wavelength temperature obtained by converting the ratio between the first and second outputs into a temperature; and to determine a temperature of the heat source based on the dual-wavelength temperature and determine a distance to the heat source from the infrared sensor based on a comparison result between the single-wavelength temperature and dual-wavelength temperature.Type: ApplicationFiled: May 31, 2017Publication date: February 1, 2018Applicant: FUJITSU LIMITEDInventors: Hironori Nishino, Yasuo MATSUMIYA
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Publication number: 20180035065Abstract: An imaging apparatus includes an image sensor including a common sensor element, the common sensor element having a plurality of output systems therefrom, and a signal processing circuit that generates an image signal from outputs of the image sensor, wherein the plurality of output systems individually include a transistor, a capacitor that stores charge in accordance with a current flowing through the sensor element via the transistor, and output circuitry that outputs a sensor signal in accordance with a voltage of the capacitor, wherein the transistors individually allow the current to flow in time periods different with each other, and the signal processing circuit does not use the sensor signals if the sensor signals do not match with each other, and the signal processing circuit uses the sensor signals for generating the image signal if the sensor signals match with each other.Type: ApplicationFiled: July 10, 2017Publication date: February 1, 2018Applicant: FUJITSU LIMITEDInventors: Hironori Nishino, Yasuo MATSUMIYA
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Publication number: 20170263168Abstract: An apparatus for image display includes: a drawing circuit configured to carry out drawing processes which include irradiating a retina with light through a pupil; a detector configured to detect scattered light generated due to reflection of light emitted by the drawing circuit around the pupil; and a stopping circuit configured to stop the drawing processes performed by the drawing circuit for a given period when the scattered light is detected by the detector.Type: ApplicationFiled: January 18, 2017Publication date: September 14, 2017Applicant: FUJITSU LIMITEDInventor: Yasuo MATSUMIYA
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Publication number: 20140225216Abstract: A photodetector includes a substrate, a first electrode layer, a first light absorbing layer, a second electrode layer, a second light absorbing layer, and a third electrode layer that are laminated on the substrate, a first electrode wire that intercouples the first electrode layer and the second electrode layer, a second electrode wire that intercouples the second electrode layer and the third electrode layer, a first diode formed at a place where the second electrode layer and the first electrode wire are mutually brought into contact, and a second diode formed at a place where the second electrode layer and the second electrode wire are mutually brought into contact.Type: ApplicationFiled: April 15, 2014Publication date: August 14, 2014Applicant: FUJITSU LIMITEDInventors: SHINICHIRO KAWAKAMI, Yasuo MATSUMIYA
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Publication number: 20120104535Abstract: A photodetector includes a substrate, a first electrode layer, a first light absorbing layer, a second electrode layer, a second light absorbing layer, and a third electrode layer that are laminated on the substrate, a first electrode wire that intercouples the first electrode layer and the second electrode layer, a second electrode wire that intercouples the second electrode layer and the third electrode layer, a first diode formed at a place where the second electrode layer and the first electrode wire are mutually brought into contact, and a second diode formed at a place where the second electrode layer and the second electrode wire are mutually brought into contact.Type: ApplicationFiled: October 27, 2011Publication date: May 3, 2012Applicant: FUJITSU LIMITEDInventors: Shinichiro KAWAKAMI, Yasuo MATSUMIYA
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Patent number: 8073241Abstract: An inspecting method increases the accuracy of a DSA (Defect Source Analysis) for thereby increasing the yield of semiconductor devices which are manufactured. For performing a DSA using data of a defect inspecting process obtained when wiring patterns are formed on a wafer and data of a VC (Voltage Contrast) inspecting process performed after the wiring patterns are formed, a rectangular DSA area is established in relation to a wiring pattern in which a nonconductive area is detected, based on the shape of the wiring pattern. For example, if three defects are detected in the defect inspecting process, then it is possible to select only at least one of those defects which affects the wiring pattern in the DSA area. Since fabrication steps can appropriately be evaluated based on the selected defect, suitable actions may be taken for any problematic fabrication step based on the evaluation of the fabrication steps.Type: GrantFiled: April 5, 2006Date of Patent: December 6, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Atsuo Fushida, Yasuo Matsumiya, Yasuhiro Suzuki, Akihiro Shimada
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Patent number: 7592623Abstract: A semiconductor device includes a substrate, a semiconductor element formed on the substrate, and a wiring connection testing structure which is formed on the substrate and which includes an electron beam irradiation area where an electron beam is irradiated so that a wiring connection is tested. The wiring connection testing structure includes an insulation layer formed on the substrate, a plurality of first pattern wirings which are formed on the insulation layer in parallel and which include the electron beam irradiation area, a second pattern wiring formed between the first pattern wirings, a third pattern wiring which is formed on a lower layer of the second pattern wiring and which is connected to the second pattern wiring, and a fourth pattern wiring which is formed on an upper layer of the third pattern wiring, is connected to the third pattern wiring, and has the electron beam irradiation area.Type: GrantFiled: April 27, 2005Date of Patent: September 22, 2009Assignee: Fujitsu Microelectronics LimitedInventor: Yasuo Matsumiya
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Publication number: 20090196490Abstract: A method, of inspecting a semiconductor device for defects, includes: acquiring an observation image of the semiconductor device, the observation image including a defect inspection object area which has a repetitive pattern; superposing a reference on the observation image thereby to form a test-mule image representing a version of the observation image in which signals have been removed from a given area, including the defect inspection area, masked with the reference ; and inspecting for defects in the test-mule image thereby to identify corresponding defects in the observation image.Type: ApplicationFiled: February 6, 2009Publication date: August 6, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventor: Yasuo MATSUMIYA
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Patent number: 7538345Abstract: A substrate inspection method includes forming, along a route extending from a peripheral portion to a central portion of an inspection area, a conducting path built up by combining a plurality of first conducting elements disposed in a first layer of a substrate, a plurality of second conducting elements disposed in a second layer of the substrate and contact holes connecting the first conducting elements and the second conducting elements between the first layer and the second layer, and detecting electrons emitted from the inspection area by irradiating the inspection area with electron beams.Type: GrantFiled: March 7, 2006Date of Patent: May 26, 2009Assignee: Fujitsu Microelectronics LimitedInventor: Yasuo Matsumiya
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Publication number: 20070069757Abstract: A substrate inspection method includes forming, along a route extending from a peripheral portion to a central portion of an inspection area, a conducting path built up by combining a plurality of first conducting elements disposed in a first layer of a substrate, a plurality of second conducting elements disposed in a second layer of the substrate and contact holes connecting the first conducting elements and the second conducting elements between the first layer and the second layer, and detecting electrons emitted from the inspection area by irradiating the inspection area with electron beams.Type: ApplicationFiled: March 7, 2006Publication date: March 29, 2007Applicant: FUJITSU LIMITEDInventor: Yasuo Matsumiya
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Publication number: 20070041631Abstract: An inspecting method increases the accuracy of a DSA for thereby increasing the yield of semiconductor devices which are manufactured. For performing a DSA using the data of a defect inspecting process obtained when wiring patterns are formed on a wafer and the dada of a VC inspecting process performed after the wiring patterns are formed, a rectangular DSA area is established in surrounding relation to a wiring pattern in which a nonconductive area is detected, based on the shape of the wiring pattern. For example, if three defects are detected in the defect inspecting process, then it is possible to select only at least one of those defects which affects the wiring pattern in the DSA area. Since fabrication steps can appropriately be evaluated based on the selected defect, suitable necessary actions or countermeasures may be taken for any problematic fabrication step based on the evaluation of the fabrication steps, so that high-performance, high-quality semiconductor devices can be manufactured.Type: ApplicationFiled: April 5, 2006Publication date: February 22, 2007Applicant: FUJITSU LIMITEDInventors: Atsuo Fushida, Yasuo Matsumiya, Yasuhiro Suzuki, Akihiro Shimada
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Publication number: 20060175607Abstract: A semiconductor device includes a substrate, a semiconductor element formed on the substrate, and a wiring connection testing structure which is formed on the substrate and which includes an electron beam irradiation area where an electron beam is irradiated so that a wiring connection is tested. The wiring connection testing structure includes an insulation layer formed on the substrate, a plurality of first pattern wirings which are formed on the insulation layer in parallel and which include the electron beam irradiation area, a second pattern wiring formed between the first pattern wirings, a third pattern wiring which is formed on a lower layer of the second pattern wiring and which is connected to the second pattern wiring, and a fourth pattern wiring which is formed on an upper layer of the third pattern wiring, is connected to the third pattern wiring, and has the electron beam irradiation area.Type: ApplicationFiled: April 27, 2005Publication date: August 10, 2006Inventor: Yasuo Matsumiya